Intel Boards

The torii.platform.vendor.altera module provides a base platform to support Intel toolchains with the Quartus and Mistral toolchains.

class torii_boards.altera.arrow_deca.ArrowDECAPlatform(*, toolchain: Literal['Quartus', 'Mistral'] = 'Quartus')

device = '10M50DA'

package = 'F484'

speed = 'C6'

suffix = 'GES'

default_clk = 'clk50'

pretty_name = 'DECA Development Kit'

description = 'Arrow Development Tools DECA Altera MAX10 Development Kit'

resources = [(resource clk50 0 (pins i M8) (clock 50000000.0) (attrs io_standard='2.5 V')), (resource clk50 1 (pins i P11) (clock 50000000.0) (attrs io_standard='3.3 V')), (resource clk50 2 (pins i N15) (clock 50000000.0) (attrs io_standard='1.5 V')), (resource clk10 0 (pins i M9) (clock 10000000.0) (attrs io_standard='2.5 V')), (resource led 0 (pins-n o C7) (attrs io_standard='1.2 V')), (resource led 1 (pins-n o C8) (attrs io_standard='1.2 V')), (resource led 2 (pins-n o A6) (attrs io_standard='1.2 V')), (resource led 3 (pins-n o B7) (attrs io_standard='1.2 V')), (resource led 4 (pins-n o C4) (attrs io_standard='1.2 V')), (resource led 5 (pins-n o A5) (attrs io_standard='1.2 V')), (resource led 6 (pins-n o B4) (attrs io_standard='1.2 V')), (resource led 7 (pins-n o C5) (attrs io_standard='1.2 V')), (resource button 0 (pins-n i H21) (attrs io_standard='1.5 V')), (resource button 1 (pins-n i H22) (attrs io_standard='1.5 V')), (resource switch 0 (pins i J21) (attrs io_standard='1.5 V')), (resource switch 1 (pins i J22) (attrs io_standard='1.5 V'))]

connectors = [(connector gpio 0 1=>W18 2=>Y18 3=>Y19 4=>AA17 5=>AA20 6=>AA19 7=>AB21 8=>AB20 9=>AB19 10=>Y16 11=>V16 12=>AB18 13=>V15 14=>W17 15=>AB17 16=>AA16 17=>AB16 18=>W16 19=>AB15 20=>W15 21=>Y14 22=>AA15 23=>AB14 24=>AA14 25=>AB13 26=>AA13 27=>AB12 28=>AA12 29=>AB11 30=>AA11 31=>AB10 32=>Y13 33=>Y11 34=>W13 35=>W12 36=>W11 37=>V12 38=>V11 39=>V13 40=>V14 41=>Y17 42=>W14 43=>U15 44=>R13), (connector gpio 1 1=>Y5 2=>Y6 3=>W6 4=>W7 5=>W8 6=>V8 7=>AB8 8=>V7 9=>R11 10=>AB7 11=>AB6 12=>AA7 13=>AA6 14=>Y7 15=>V10 16=>U7 17=>W9 18=>W5 19=>R9 20=>W4 21=>P9 22=>V17 23=>W3)]

toolchain_program(products: BuildProducts, name: str) → None

Extract bitstream for fragment name from products and download it to a target.

property file_templates

class torii_boards.altera.chameleon96.Chameleon96Platform(*, toolchain: Literal['Quartus', 'Mistral'] = 'Quartus')

device = '5CSEBA6'

package = 'U19'

speed = 'I7'

default_clk = 'cyclonev_oscillator'

pretty_name = 'Chameleon96'

description = 'Altera Cyclone V SoC Development Board'

resources = [(resource led 0 (pins o Y19) (attrs io_standard='2.5 V')), (resource led 1 (pins o Y20) (attrs io_standard='2.5 V')), (resource tda19988 0 (subsignal vpa (pins o W8 W7 V6 V5 U6)) (subsignal vpb (pins o AB5 AA5 AA8 AB8 AB9 Y11)) (subsignal vpc (pins o W6 Y5 AB7 AA7 AA6)) (subsignal pclk (pins o AB10)) (subsignal hsync (pins o V10)) (subsignal vsync (pins o V7)) (subsignal de (pins o Y8)) (attrs io_standard='1.8 V')), (resource tda19988_i2c 0 (subsignal scl (pins io U7)) (subsignal sda (pins io U10)) (attrs io_standard='1.8 V')), (resource tda19988_i2s 0 (subsignal mclk (pins o V11)) (subsignal txd (pins o AA11)) (subsignal txc (pins o W11)) (subsignal txfs (pins o V9)) (attrs io_standard='1.8 V')), (resource wifi_1bit 0 (subsignal clk (pins o AB20)) (subsignal cmd (pins o AB18)) (subsignal dat (pins io Y14)) (subsignal ecd (pins i AB15)) (attrs io_standard='1.8 V')), (resource wifi_4bit 0 (subsignal clk (pins o AB20)) (subsignal cmd (pins o AB18)) (subsignal dat (pins io Y14 AB19 AA18 AB15)) (attrs io_standard='1.8 V')), (resource wifi_spi 0 (subsignal cs (pins-n io AB15)) (subsignal clk (pins o AB20)) (subsignal copi (pins o AB18)) (subsignal cipo (pins i Y14)) (attrs io_standard='1.8 V')), (resource bt 0 (subsignal host_wake (pins o AB12)) (attrs io_standard='1.8 V')), (resource bt_i2s 0 (subsignal txd (pins o Y15)) (subsignal rxd (pins i Y16)) (subsignal txc (pins i AA13)) (subsignal txfs (pins i AB13)) (attrs io_standard='1.8 V')), (resource bt_uart 0 (subsignal rx (pins i AB14)) (subsignal tx (pins o AA15)) (subsignal rts (pins o AA16)) (subsignal cts (pins i AB17)) (attrs io_standard='1.8 V'))]

connectors = [(connector J 3 3=>Y13 5=>W14 7=>C5 9=>C6 10=>-- 15=>E5 17=>F5 19=>A6- 20=>A5 28=>--), (connector J 8 2=>V16 4=>U17 8=>V17 10=>W18- 13=>U18 14=>W12 15=>V19 19=>-- 28=>-- 37=>-- 46=>--)]

toolchain_program(products: BuildProducts, name: str) → None

Extract bitstream for fragment name from products and download it to a target.

class torii_boards.altera.de0_cv.DE0CVPlatform(*, toolchain: Literal['Quartus', 'Mistral'] = 'Quartus')

device = '5CEBA4'

package = 'F23'

speed = 'C7'

default_clk = 'clk50'

pretty_name = 'DE0-CV'

description = 'terasIC DE0-CV Altera Cyclone V Development Board'

resources = [(resource clk50 0 (pins i M9) (clock 50000000.0) (attrs io_standard='3.3-V LVTTL')), (resource clk50 1 (pins i H13) (clock 50000000.0) (attrs io_standard='3.3-V LVTTL')), (resource clk50 2 (pins i E10) (clock 50000000.0) (attrs io_standard='3.3-V LVTTL')), (resource clk50 3 (pins i V15) (clock 50000000.0) (attrs io_standard='3.3-V LVTTL')), (resource led 0 (pins-n o AA2) (attrs io_standard='3.3-V LVTTL')), (resource led 1 (pins-n o AA1) (attrs io_standard='3.3-V LVTTL')), (resource led 2 (pins-n o W2) (attrs io_standard='3.3-V LVTTL')), (resource led 3 (pins-n o Y3) (attrs io_standard='3.3-V LVTTL')), (resource led 4 (pins-n o N2) (attrs io_standard='3.3-V LVTTL')), (resource led 5 (pins-n o N1) (attrs io_standard='3.3-V LVTTL')), (resource led 6 (pins-n o U2) (attrs io_standard='3.3-V LVTTL')), (resource led 7 (pins-n o U1) (attrs io_standard='3.3-V LVTTL')), (resource led 8 (pins-n o L2) (attrs io_standard='3.3-V LVTTL')), (resource led 9 (pins-n o L1) (attrs io_standard='3.3-V LVTTL')), (resource button 0 (pins-n i U7) (attrs io_standard='3.3-V LVTTL')), (resource button 1 (pins-n i W9) (attrs io_standard='3.3-V LVTTL')), (resource button 2 (pins-n i M7) (attrs io_standard='3.3-V LVTTL')), (resource button 3 (pins-n i M6) (attrs io_standard='3.3-V LVTTL')), (resource switch 0 (pins i U13) (attrs io_standard='3.3-V LVTTL')), (resource switch 1 (pins i V13) (attrs io_standard='3.3-V LVTTL')), (resource switch 2 (pins i T13) (attrs io_standard='3.3-V LVTTL')), (resource switch 3 (pins i T12) (attrs io_standard='3.3-V LVTTL')), (resource switch 4 (pins i AA15) (attrs io_standard='3.3-V LVTTL')), (resource switch 5 (pins i AB15) (attrs io_standard='3.3-V LVTTL')), (resource switch 6 (pins i AA14) (attrs io_standard='3.3-V LVTTL')), (resource switch 7 (pins i AA13) (attrs io_standard='3.3-V LVTTL')), (resource switch 8 (pins i AB13) (attrs io_standard='3.3-V LVTTL')), (resource switch 9 (pins i AB12) (attrs io_standard='3.3-V LVTTL')), (resource display_7seg 0 (subsignal a (pins-n o U21)) (subsignal b (pins-n o V21)) (subsignal c (pins-n o W22)) (subsignal d (pins-n o W21)) (subsignal e (pins-n o Y22)) (subsignal f (pins-n o Y21)) (subsignal g (pins-n o AA22)) (attrs io_standard='3.3-V LVTTL')), (resource display_7seg 1 (subsignal a (pins-n o AA20)) (subsignal b (pins-n o AB20)) (subsignal c (pins-n o AA19)) (subsignal d (pins-n o AA18)) (subsignal e (pins-n o AB18)) (subsignal f (pins-n o AA17)) (subsignal g (pins-n o U22)) (attrs io_standard='3.3-V LVTTL')), (resource display_7seg 2 (subsignal a (pins-n o Y19)) (subsignal b (pins-n o AB17)) (subsignal c (pins-n o AA10)) (subsignal d (pins-n o Y14)) (subsignal e (pins-n o V14)) (subsignal f (pins-n o AB22)) (subsignal g (pins-n o AB21)) (attrs io_standard='3.3-V LVTTL')), (resource display_7seg 3 (subsignal a (pins-n o Y16)) (subsignal b (pins-n o W16)) (subsignal c (pins-n o Y17)) (subsignal d (pins-n o V16)) (subsignal e (pins-n o U17)) (subsignal f (pins-n o V18)) (subsignal g (pins-n o V19)) (attrs io_standard='3.3-V LVTTL')), (resource display_7seg 4 (subsignal a (pins-n o U20)) (subsignal b (pins-n o Y20)) (subsignal c (pins-n o V20)) (subsignal d (pins-n o U16)) (subsignal e (pins-n o U15)) (subsignal f (pins-n o Y15)) (subsignal g (pins-n o P9)) (attrs io_standard='3.3-V LVTTL')), (resource display_7seg 5 (subsignal a (pins-n o N9)) (subsignal b (pins-n o M8)) (subsignal c (pins-n o T14)) (subsignal d (pins-n o P14)) (subsignal e (pins-n o C1)) (subsignal f (pins-n o C2)) (subsignal g (pins-n o W19)) (attrs io_standard='3.3-V LVTTL')), (resource vga 0 (subsignal r (pins o A9 B10 C9 A5)) (subsignal g (pins o L7 K7 J7 J8)) (subsignal b (pins o B6 B7 A8 A7)) (subsignal hs (pins o H8)) (subsignal vs (pins o G8)) (attrs io_standard='3.3-V LVTTL')), (resource ps2 0 (subsignal clk (pins i D3)) (subsignal dat (pins io G2)) (attrs io_standard='3.3-V LVTTL')), (resource ps2 1 (subsignal clk (pins i E2)) (subsignal dat (pins io G1)) (attrs io_standard='3.3-V LVTTL')), (resource sd_card_1bit 0 (subsignal clk (pins o H11)) (subsignal cmd (pins o B11)) (subsignal dat (pins io K9)) (subsignal ecd (pins i C11)) (attrs io_standard='3.3-V LVTTL')), (resource sd_card_4bit 0 (subsignal clk (pins o H11)) (subsignal cmd (pins o B11)) (subsignal dat (pins io K9 D12 E12 C11)) (attrs io_standard='3.3-V LVTTL')), (resource sd_card_spi 0 (subsignal cs (pins-n io C11)) (subsignal clk (pins o H11)) (subsignal copi (pins o B11)) (subsignal cipo (pins i K9)) (attrs io_standard='3.3-V LVTTL')), (resource sdram 0 (subsignal clk (pins o AB11)) (subsignal clk_en (pins o R6)) (subsignal cs (pins-n o U6)) (subsignal we (pins-n o AB5)) (subsignal ras (pins-n o AB6)) (subsignal cas (pins-n o V6)) (subsignal ba (pins o T7 AB7)) (subsignal a (pins o W8 T8 U11 Y10 N6 AB10 P12 P7 P8 R5 U8 P6 R7)) (subsignal dq (pins io Y9 T10 R9 Y11 R10 R11 R12 AA12 AA9 AB8 AA8 AA7 V10 V9 U10 T9)) (subsignal dqm (pins o U12 N8)) (attrs io_standard='3.3-V LVCMOS'))]

connectors = [(connector j 1 1=>N16 2=>B16 3=>M16 4=>C16 5=>D17 6=>K20 7=>K21 8=>K22 9=>M20 10=>M21 13=>N21 14=>R22 15=>R21 16=>T22 17=>N20 18=>N19 19=>M22 20=>P19 21=>L22 22=>P17 23=>P16 24=>M18 25=>L18 26=>L17 27=>L19 28=>K17 31=>K19 32=>P18 33=>R15 34=>R17 35=>R16 36=>T20 37=>T19 38=>T18 39=>T17 40=>T15), (connector j 2 1=>H16 2=>A12 3=>H15 4=>B12 5=>A13 6=>B13 7=>C13 8=>D13 9=>G18 10=>G17 13=>H18 14=>J18 15=>J19 16=>G11 17=>H10 18=>J11 19=>H14 20=>A15 21=>J13 22=>L8 23=>A14 24=>B15 25=>C15 26=>E14 27=>E15 28=>E16 31=>F14 32=>F15 33=>F13 34=>F12 35=>G16 36=>G15 37=>G13 38=>G12 39=>J17 40=>K16)]

toolchain_program(products: BuildProducts, name: str) → None

Extract bitstream for fragment name from products and download it to a target.

class torii_boards.altera.de0.DE0Platform(*, toolchain: Literal['Quartus', 'Mistral'] = 'Quartus')

device = 'EP3C16'

package = 'F484'

speed = 'C6'

default_clk = 'clk50'

pretty_name = 'DE0'

description = 'terasIC DE0 Altera Cyclone III Development Board'

resources = [(resource clk50 0 (pins i G21) (clock 50000000.0) (attrs io_standard='3.3-V LVTTL')), (resource clk50 1 (pins i B12) (clock 50000000.0) (attrs io_standard='3.3-V LVTTL')), (resource led 0 (pins o J1) (attrs io_standard='3.3-V LVTTL')), (resource led 1 (pins o J2) (attrs io_standard='3.3-V LVTTL')), (resource led 2 (pins o J3) (attrs io_standard='3.3-V LVTTL')), (resource led 3 (pins o H1) (attrs io_standard='3.3-V LVTTL')), (resource led 4 (pins o F2) (attrs io_standard='3.3-V LVTTL')), (resource led 5 (pins o E1) (attrs io_standard='3.3-V LVTTL')), (resource led 6 (pins o C1) (attrs io_standard='3.3-V LVTTL')), (resource led 7 (pins o C2) (attrs io_standard='3.3-V LVTTL')), (resource led 8 (pins o B2) (attrs io_standard='3.3-V LVTTL')), (resource led 9 (pins o B1) (attrs io_standard='3.3-V LVTTL')), (resource button 0 (pins-n i H2) (attrs io_standard='3.3-V LVTTL')), (resource button 1 (pins-n i G3) (attrs io_standard='3.3-V LVTTL')), (resource button 2 (pins-n i F1) (attrs io_standard='3.3-V LVTTL')), (resource switch 0 (pins i J6) (attrs io_standard='3.3-V LVTTL')), (resource switch 1 (pins i H5) (attrs io_standard='3.3-V LVTTL')), (resource switch 2 (pins i H6) (attrs io_standard='3.3-V LVTTL')), (resource switch 3 (pins i G4) (attrs io_standard='3.3-V LVTTL')), (resource switch 4 (pins i G5) (attrs io_standard='3.3-V LVTTL')), (resource switch 5 (pins i J7) (attrs io_standard='3.3-V LVTTL')), (resource switch 6 (pins i H7) (attrs io_standard='3.3-V LVTTL')), (resource switch 7 (pins i E3) (attrs io_standard='3.3-V LVTTL')), (resource switch 8 (pins i E4) (attrs io_standard='3.3-V LVTTL')), (resource switch 9 (pins i D2) (attrs io_standard='3.3-V LVTTL')), (resource display_7seg 0 (subsignal a (pins-n o E11)) (subsignal b (pins-n o F11)) (subsignal c (pins-n o H12)) (subsignal d (pins-n o H13)) (subsignal e (pins-n o G12)) (subsignal f (pins-n o F12)) (subsignal g (pins-n o F13)) (subsignal dp (pins-n o D13)) (attrs io_standard='3.3-V LVTTL')), (resource display_7seg 1 (subsignal a (pins-n o A13)) (subsignal b (pins-n o B13)) (subsignal c (pins-n o C13)) (subsignal d (pins-n o A14)) (subsignal e (pins-n o B14)) (subsignal f (pins-n o E14)) (subsignal g (pins-n o A15)) (subsignal dp (pins-n o B15)) (attrs io_standard='3.3-V LVTTL')), (resource display_7seg 2 (subsignal a (pins-n o D15)) (subsignal b (pins-n o A16)) (subsignal c (pins-n o B16)) (subsignal d (pins-n o E15)) (subsignal e (pins-n o A17)) (subsignal f (pins-n o B17)) (subsignal g (pins-n o F14)) (subsignal dp (pins-n o A18)) (attrs io_standard='3.3-V LVTTL')), (resource display_7seg 3 (subsignal a (pins-n o B18)) (subsignal b (pins-n o F15)) (subsignal c (pins-n o A19)) (subsignal d (pins-n o B19)) (subsignal e (pins-n o C19)) (subsignal f (pins-n o D19)) (subsignal g (pins-n o G15)) (subsignal dp (pins-n o G16)) (attrs io_standard='3.3-V LVTTL')), (resource uart 0 (subsignal rx (pins i U22)) (subsignal tx (pins o U21)) (subsignal rts (pins i V22)) (subsignal cts (pins o V21)) (attrs io_standard='3.3-V LVTTL')), (resource display_hd44780 0 (subsignal e (pins o E21)) (subsignal d (pins io D22 D21 C22 C21 B22 B21 D20 C20)) (subsignal rw (pins o E22)) (subsignal rs (pins o F22)) (subsignal bl (pins o F21)) (attrs io_standard='3.3-V LVTTL')), (resource vga 0 (subsignal r (pins o H19 H17 H20 H21)) (subsignal g (pins o H22 J17 K17 J21)) (subsignal b (pins o K22 K21 J22 K18)) (subsignal hs (pins o L21)) (subsignal vs (pins o L22)) (attrs io_standard='3.3-V LVTTL')), (resource ps2 0 (subsignal clk (pins i P22)) (subsignal dat (pins io P21)) (attrs io_standard='3.3-V LVTTL')), (resource ps2 1 (subsignal clk (pins i R21)) (subsignal dat (pins io R22)) (attrs io_standard='3.3-V LVTTL')), (resource sd_card_1bit 0 (subsignal wp (pins-n i W20)) (subsignal clk (pins o Y21)) (subsignal cmd (pins o Y22)) (subsignal dat (pins io AA22)) (subsignal ecd (pins i W21)) (attrs io_standard='3.3-V LVTTL')), (resource sd_card_spi 0 (subsignal wp (pins-n i W20)) (subsignal cs (pins-n io W21)) (subsignal clk (pins o Y21)) (subsignal copi (pins o Y22)) (subsignal cipo (pins i AA22)) (attrs io_standard='3.3-V LVTTL')), (resource sdram 0 (subsignal clk (pins o E5)) (subsignal clk_en (pins o E6)) (subsignal cs (pins-n o G7)) (subsignal we (pins-n o D6)) (subsignal ras (pins-n o F7)) (subsignal cas (pins-n o G8)) (subsignal ba (pins o B5 A4)) (subsignal a (pins o C4 A3 B3 C3 A5 C6 B6 A6 C7 B7 B4 A7 C8)) (subsignal dq (pins io D10 G10 H10 E9 F9 G9 H9 F8 A8 B9 A9 C10 B10 A10 E10 F10)) (subsignal dqm (pins o E7 B8)) (attrs io_standard='3.3-V LVTTL')), (resource nor_flash_8bit 0 (subsignal rst (pins o R1)) (subsignal cs (pins-n o N8)) (subsignal oe (pins-n o R6)) (subsignal we (pins-n o P4)) (subsignal wp (pins-n o T3)) (subsignal rdy (pins i M7)) (subsignal byte (pins-n o AA1)) (subsignal a (pins o Y2 P7 P5 P6 N7 N5 N6 M8 M4 P2 N2 N1 M3 M2 M1 L7 L6 AA2 M5 M6 P1 P3 R2)) (subsignal dq (pins io R7 P8 R8 U1 V2 V3 W1 Y1))), (resource nor_flash_16bit 0 (subsignal rst (pins o R1)) (subsignal cs (pins-n o N8)) (subsignal oe (pins-n o R6)) (subsignal we (pins-n o P4)) (subsignal wp (pins-n o T3)) (subsignal rdy (pins i M7)) (subsignal byte (pins-n o AA1)) (subsignal a (pins o P7 P5 P6 N7 N5 N6 M8 M4 P2 N2 N1 M3 M2 M1 L7 L6 AA2 M5 M6 P1 P3 R2)) (subsignal dq (pins io R7 P8 R8 U1 V2 V3 W1 Y1 T5 T7 T4 U2 V1 V4 W2 Y2)))]

connectors = [(connector j 4 1=>AB12 2=>AB16 3=>AA12 4=>AA16 5=>AA15 6=>AB15 7=>AA14 8=>AB14 9=>AB13 10=>AA13 13=>AB10 14=>AA10 15=>AB8 16=>AA8 17=>AB5 18=>AA5 19=>AB3 20=>AB4 21=>AA3 22=>AA4 23=>V14 24=>U14 25=>Y13 26=>W13 27=>U13 28=>V12 31=>R10 32=>V11 33=>Y10 34=>W10 35=>T8 36=>V8 37=>W7 38=>W6 39=>V5 40=>U7), (connector j 5 1=>AB11 2=>AA20 3=>AA11 4=>AB20 5=>AA19 6=>AB19 7=>AB18 8=>AA18 9=>AA17 10=>AB17 13=>Y17 14=>W17 15=>U15 16=>T15 17=>W15 18=>V15 19=>R16 20=>AB9 21=>T16 22=>AA9 23=>AA7 24=>AB7 25=>T14 26=>R14 27=>U12 28=>T12 31=>R11 32=>R12 33=>U10 34=>T10 35=>U9 36=>T9 37=>Y7 38=>U8 39=>V6 40=>V7)]

toolchain_program(products: BuildProducts, name: str) → None

Extract bitstream for fragment name from products and download it to a target.

class torii_boards.altera.de1_soc.DE1SoCPlatform(*, toolchain: Literal['Quartus', 'Mistral'] = 'Quartus')

device = '5CSEMA5'

package = 'F31'

speed = 'C6'

default_clk = 'clk50'

pretty_name = 'DE1-SoC'

description = 'terasIC DE1-SoC Altera Cyclone V SoC Development Board'

resources = [(resource clk50 0 (pins i AF14) (clock 50000000.0) (attrs io_standard='3.3-V LVTTL')), (resource clk50 1 (pins i AA16) (clock 50000000.0) (attrs io_standard='3.3-V LVTTL')), (resource clk50 2 (pins i Y26) (clock 50000000.0) (attrs io_standard='3.3-V LVTTL')), (resource clk50 3 (pins i K14) (clock 50000000.0) (attrs io_standard='3.3-V LVTTL')), (resource led 0 (pins o V16) (attrs io_standard='3.3-V LVTTL')), (resource led 1 (pins o W16) (attrs io_standard='3.3-V LVTTL')), (resource led 2 (pins o V17) (attrs io_standard='3.3-V LVTTL')), (resource led 3 (pins o V18) (attrs io_standard='3.3-V LVTTL')), (resource led 4 (pins o W17) (attrs io_standard='3.3-V LVTTL')), (resource led 5 (pins o W19) (attrs io_standard='3.3-V LVTTL')), (resource led 6 (pins o Y19) (attrs io_standard='3.3-V LVTTL')), (resource led 7 (pins o W20) (attrs io_standard='3.3-V LVTTL')), (resource led 8 (pins o W21) (attrs io_standard='3.3-V LVTTL')), (resource led 9 (pins o Y21) (attrs io_standard='3.3-V LVTTL')), (resource button 0 (pins-n i AA14) (attrs io_standard='3.3-V LVTTL')), (resource button 1 (pins-n i AA15) (attrs io_standard='3.3-V LVTTL')), (resource button 2 (pins-n i W15) (attrs io_standard='3.3-V LVTTL')), (resource button 3 (pins-n i Y16) (attrs io_standard='3.3-V LVTTL')), (resource switch 0 (pins i AB12) (attrs io_standard='3.3-V LVTTL')), (resource switch 1 (pins i AC12) (attrs io_standard='3.3-V LVTTL')), (resource switch 2 (pins i AF9) (attrs io_standard='3.3-V LVTTL')), (resource switch 3 (pins i AF10) (attrs io_standard='3.3-V LVTTL')), (resource switch 4 (pins i AD11) (attrs io_standard='3.3-V LVTTL')), (resource switch 5 (pins i AD12) (attrs io_standard='3.3-V LVTTL')), (resource switch 6 (pins i AE11) (attrs io_standard='3.3-V LVTTL')), (resource switch 7 (pins i AC9) (attrs io_standard='3.3-V LVTTL')), (resource switch 8 (pins i AD10) (attrs io_standard='3.3-V LVTTL')), (resource switch 9 (pins i AE12) (attrs io_standard='3.3-V LVTTL')), (resource display_7seg 0 (subsignal a (pins-n o AE26)) (subsignal b (pins-n o AE27)) (subsignal c (pins-n o AE28)) (subsignal d (pins-n o AG27)) (subsignal e (pins-n o AF28)) (subsignal f (pins-n o AG28)) (subsignal g (pins-n o AH28)) (attrs io_standard='3.3-V LVTTL')), (resource display_7seg 1 (subsignal a (pins-n o AJ29)) (subsignal b (pins-n o AH29)) (subsignal c (pins-n o AH30)) (subsignal d (pins-n o AG30)) (subsignal e (pins-n o AF29)) (subsignal f (pins-n o AF30)) (subsignal g (pins-n o AD27)) (attrs io_standard='3.3-V LVTTL')), (resource display_7seg 2 (subsignal a (pins-n o AB23)) (subsignal b (pins-n o AE29)) (subsignal c (pins-n o AD29)) (subsignal d (pins-n o AC28)) (subsignal e (pins-n o AD30)) (subsignal f (pins-n o AC29)) (subsignal g (pins-n o AC30)) (attrs io_standard='3.3-V LVTTL')), (resource display_7seg 3 (subsignal a (pins-n o AD26)) (subsignal b (pins-n o AC27)) (subsignal c (pins-n o AD25)) (subsignal d (pins-n o AC25)) (subsignal e (pins-n o AB28)) (subsignal f (pins-n o AB25)) (subsignal g (pins-n o AB22)) (attrs io_standard='3.3-V LVTTL')), (resource display_7seg 4 (subsignal a (pins-n o AA24)) (subsignal b (pins-n o Y23)) (subsignal c (pins-n o Y24)) (subsignal d (pins-n o W22)) (subsignal e (pins-n o W24)) (subsignal f (pins-n o V23)) (subsignal g (pins-n o W25)) (attrs io_standard='3.3-V LVTTL')), (resource display_7seg 5 (subsignal a (pins-n o V25)) (subsignal b (pins-n o AA28)) (subsignal c (pins-n o Y27)) (subsignal d (pins-n o AB27)) (subsignal e (pins-n o AB26)) (subsignal f (pins-n o AA26)) (subsignal g (pins-n o AA25)) (attrs io_standard='3.3-V LVTTL'))]

connectors = [(connector gpio 0 1=>AC18 2=>Y17 3=>AD17 4=>Y18 5=>AK16 6=>AK18 7=>AK19 8=>AJ19 9=>AJ17 10=>AJ16 13=>AH18 14=>AH17 15=>AG16 16=>AE16 17=>AF16 18=>AG17 19=>AA18 20=>AA19 21=>AE17 22=>AC20 23=>AH19 24=>AJ20 25=>AH20 26=>AK21 27=>AD19 28=>AD20 31=>AE18 32=>AE19 33=>AF20 34=>AF21 35=>AF19 36=>AG21 37=>AF18 38=>AG20 39=>AG18 40=>AJ21), (connector gpio 1 1=>AB17 2=>AA21 3=>AB21 4=>AC23 5=>AD24 6=>AE23 7=>AE24 8=>AF25 9=>AF26 10=>AG25 13=>AG26 14=>AH24 15=>AH27 16=>AJ27 17=>AK29 18=>AK28 19=>AK27 20=>AJ26 21=>AK26 22=>AH25 23=>AJ25 24=>AJ24 25=>AK24 26=>AG23 27=>AK23 28=>AH23 31=>AK22 32=>AJ22 33=>AH22 34=>AG22 35=>AF24 36=>AF23 37=>AE22 38=>AD21 39=>AA20 40=>AC22)]

toolchain_program(products: BuildProducts, name: str) → None

Extract bitstream for fragment name from products and download it to a target.

class torii_boards.altera.de10_lite.DE10LitePlatform(*, toolchain: Literal['Quartus', 'Mistral'] = 'Quartus')

device = '10M50DA'

package = 'F484'

speed = 'C7'

suffix = 'G'

default_clk = 'clk50'

pretty_name = 'DE10-Lite'

description = 'terasIC DE10-Lite Altera MAX 10 Development Board'

resources = [(resource clk10 0 (pins i N5) (clock 50000000.0) (attrs io_standard='3.3-V LVTTL')), (resource clk50 0 (pins i P11) (clock 50000000.0) (attrs io_standard='3.3-V LVTTL')), (resource clk50 1 (pins i N14) (clock 50000000.0) (attrs io_standard='3.3-V LVTTL')), (resource led 0 (pins o A8) (attrs io_standard='3.3-V LVTTL')), (resource led 1 (pins o A9) (attrs io_standard='3.3-V LVTTL')), (resource led 2 (pins o A10) (attrs io_standard='3.3-V LVTTL')), (resource led 3 (pins o B10) (attrs io_standard='3.3-V LVTTL')), (resource led 4 (pins o D13) (attrs io_standard='3.3-V LVTTL')), (resource led 5 (pins o C13) (attrs io_standard='3.3-V LVTTL')), (resource led 6 (pins o E14) (attrs io_standard='3.3-V LVTTL')), (resource led 7 (pins o D14) (attrs io_standard='3.3-V LVTTL')), (resource led 8 (pins o A11) (attrs io_standard='3.3-V LVTTL')), (resource led 9 (pins o B11) (attrs io_standard='3.3-V LVTTL')), (resource button 0 (pins-n i B8) (attrs io_standard='3.3-V LVTTL')), (resource button 1 (pins-n i A7) (attrs io_standard='3.3-V LVTTL')), (resource switch 0 (pins i C10) (attrs io_standard='3.3-V LVTTL')), (resource switch 1 (pins i C11) (attrs io_standard='3.3-V LVTTL')), (resource switch 2 (pins i D12) (attrs io_standard='3.3-V LVTTL')), (resource switch 3 (pins i C12) (attrs io_standard='3.3-V LVTTL')), (resource switch 4 (pins i A12) (attrs io_standard='3.3-V LVTTL')), (resource switch 5 (pins i B12) (attrs io_standard='3.3-V LVTTL')), (resource switch 6 (pins i A13) (attrs io_standard='3.3-V LVTTL')), (resource switch 7 (pins i A14) (attrs io_standard='3.3-V LVTTL')), (resource switch 8 (pins i B14) (attrs io_standard='3.3-V LVTTL')), (resource switch 9 (pins i F15) (attrs io_standard='3.3-V LVTTL')), (resource display_7seg 0 (subsignal a (pins-n o C14)) (subsignal b (pins-n o E15)) (subsignal c (pins-n o C15)) (subsignal d (pins-n o C16)) (subsignal e (pins-n o E16)) (subsignal f (pins-n o D17)) (subsignal g (pins-n o C17)) (subsignal dp (pins-n o D15)) (attrs io_standard='3.3-V LVTTL')), (resource display_7seg 1 (subsignal a (pins-n o C18)) (subsignal b (pins-n o D18)) (subsignal c (pins-n o E18)) (subsignal d (pins-n o B16)) (subsignal e (pins-n o A17)) (subsignal f (pins-n o A18)) (subsignal g (pins-n o B17)) (subsignal dp (pins-n o A16)) (attrs io_standard='3.3-V LVTTL')), (resource display_7seg 2 (subsignal a (pins-n o B20)) (subsignal b (pins-n o A20)) (subsignal c (pins-n o B19)) (subsignal d (pins-n o A21)) (subsignal e (pins-n o B21)) (subsignal f (pins-n o C22)) (subsignal g (pins-n o B22)) (subsignal dp (pins-n o A19)) (attrs io_standard='3.3-V LVTTL')), (resource display_7seg 3 (subsignal a (pins-n o F21)) (subsignal b (pins-n o E22)) (subsignal c (pins-n o E21)) (subsignal d (pins-n o C19)) (subsignal e (pins-n o C20)) (subsignal f (pins-n o D19)) (subsignal g (pins-n o E17)) (subsignal dp (pins-n o D22)) (attrs io_standard='3.3-V LVTTL')), (resource display_7seg 4 (subsignal a (pins-n o F18)) (subsignal b (pins-n o E20)) (subsignal c (pins-n o E19)) (subsignal d (pins-n o J18)) (subsignal e (pins-n o H19)) (subsignal f (pins-n o F19)) (subsignal g (pins-n o F20)) (subsignal dp (pins-n o F17)) (attrs io_standard='3.3-V LVTTL')), (resource display_7seg 5 (subsignal a (pins-n o J20)) (subsignal b (pins-n o K20)) (subsignal c (pins-n o L18)) (subsignal d (pins-n o N18)) (subsignal e (pins-n o M20)) (subsignal f (pins-n o N19)) (subsignal g (pins-n o N20)) (subsignal dp (pins-n o L19)) (attrs io_standard='3.3-V LVTTL')), (resource uart 0 (subsignal rx (pins i V10)) (subsignal tx (pins o W10)) (attrs io_standard='3.3-V LVTTL')), (resource sdram 0 (subsignal clk (pins o L14)) (subsignal cs (pins-n o U20)) (subsignal we (pins-n o V20)) (subsignal ras (pins-n o U22)) (subsignal cas (pins-n o U21)) (subsignal ba (pins o T21 T22)) (subsignal a (pins o U17 W19 V18 U18 U19 T18 T19 R18 P18 P19 T20 P20 R20)) (subsignal dq (pins io Y21 Y20 AA22 AA21 Y22 W22 W20 V21 P21 J22 H21 H22 G22 G20 G19 F22)) (subsignal dqm (pins o V22 J21)) (attrs io_standard='3.3-V LVCMOS')), (resource vga 0 (subsignal r (pins o AA1 V1 Y2 Y1)) (subsignal g (pins o W1 T2 R2 R1)) (subsignal b (pins o P1 T1 P4 N2)) (subsignal hs (pins o N3)) (subsignal vs (pins o N1)) (attrs io_standard='3.3-V LVTTL'))]

connectors = [(connector gpio 0 1=>V10 2=>W10 3=>V9 4=>W9 5=>V8 6=>W8 7=>V7 8=>W7 9=>W6 10=>V5 11=>W5 12=>AA15 13=>AA14 14=>W13 15=>W12 16=>AB13 17=>AB12 18=>Y11 19=>AB11 20=>W11 21=>AB10 22=>AA10 23=>AA9 24=>Y8 25=>AA8 26=>Y7 27=>AA7 28=>Y6 29=>AA6 30=>Y5 31=>AA5 32=>Y4 33=>AB3 34=>Y3 35=>AB2 36=>AA2), (connector gpio 5 1=>AB5 2=>AB6 3=>AB7 4=>AB8 5=>AB9 6=>Y10 7=>AA11 8=>AA12 9=>AB17 10=>AA17 11=>AB19 12=>AA19 13=>Y19 14=>AB20 15=>AB21 16=>AA20 17=>F16)]

toolchain_program(products: BuildProducts, name: str) → None

Extract bitstream for fragment name from products and download it to a target.

class torii_boards.altera.de10_nano.DE10NanoPlatform(*, toolchain: Literal['Quartus', 'Mistral'] = 'Quartus')

device = '5CSEBA6'

package = 'U23'

speed = 'I7'

default_clk = 'clk50'

pretty_name = 'DE10-Nano'

description = 'terasIC DE10-Nano Altera Cyclone V Development Board'

resources = [(resource clk50 0 (pins i V11) (clock 50000000.0) (attrs io_standard='3.3-V LVTTL')), (resource clk50 1 (pins i Y13) (clock 50000000.0) (attrs io_standard='3.3-V LVTTL')), (resource clk50 2 (pins i E11) (clock 50000000.0) (attrs io_standard='3.3-V LVTTL')), (resource led 0 (pins o W15) (attrs io_standard='3.3-V LVTTL')), (resource led 1 (pins o AA24) (attrs io_standard='3.3-V LVTTL')), (resource led 2 (pins o V16) (attrs io_standard='3.3-V LVTTL')), (resource led 3 (pins o V15) (attrs io_standard='3.3-V LVTTL')), (resource led 4 (pins o AF26) (attrs io_standard='3.3-V LVTTL')), (resource led 5 (pins o AE26) (attrs io_standard='3.3-V LVTTL')), (resource led 6 (pins o Y16) (attrs io_standard='3.3-V LVTTL')), (resource led 7 (pins o AA23) (attrs io_standard='3.3-V LVTTL')), (resource button 0 (pins-n i AH17) (attrs io_standard='3.3-V LVTTL')), (resource button 1 (pins-n i AH16) (attrs io_standard='3.3-V LVTTL')), (resource switch 0 (pins i Y24) (attrs io_standard='3.3-V LVTTL')), (resource switch 1 (pins i W24) (attrs io_standard='3.3-V LVTTL')), (resource switch 2 (pins i W21) (attrs io_standard='3.3-V LVTTL')), (resource switch 3 (pins i W20) (attrs io_standard='3.3-V LVTTL')), (resource uart 0 (subsignal rx (pins i AG13)) (subsignal tx (pins o AF13)) (attrs io_standard='3.3-V LVTTL')), (resource spi 0 (subsignal cs (pins-n o U9)) (subsignal clk (pins o V10)) (subsignal copi (pins o AC4)) (subsignal cipo (pins i AD4)) (attrs io_standard='3.3-V LVTTL')), (resource adv7513 0 (subsignal tx_d_r (pins o AD12 AE12 W8 Y8 AD11 AD10 AE11 Y5)) (subsignal tx_d_g (pins o AF10 Y4 AE9 AB4 AE7 AF6 AF8 AF5)) (subsignal tx_d_b (pins o AE4 AH2 AH4 AH5 AH6 AG6 AF9 AE8)) (subsignal tx_clk (pins o AG5)) (subsignal tx_de (pins o AD19)) (subsignal tx_hs (pins o T8)) (subsignal tx_vs (pins o V13)) (subsignal tx_int (pins i AF11)) (subsignal i2s0 (pins o T13)) (subsignal mclk (pins o U11)) (subsignal lrclk (pins o T11)) (subsignal sclk (pins o T12)) (subsignal scl (pins io U10)) (subsignal sda (pins io AA4)) (attrs io_standard='3.3-V LVTTL'))]

connectors = [(connector gpio 0 1=>V12 2=>E8 3=>W12 4=>D11 5=>D8 6=>AH13 7=>AF7 8=>AH14 9=>AF4 10=>AH3 13=>AD5 14=>AG14 15=>AE23 16=>AE6 17=>AD23 18=>AE24 19=>D12 20=>AD20 21=>C12 22=>AD17 23=>AC23 24=>AC22 25=>Y19 26=>AB23 27=>AA19 28=>W11 31=>AA18 32=>W14 33=>Y18 34=>Y17 35=>AB25 36=>AB26 37=>Y11 38=>AA26 39=>AA13 40=>AA11), (connector gpio 1 1=>Y15 2=>AC24 3=>AA15 4=>AD26 5=>AG28 6=>AF28 7=>AE25 8=>AF27 9=>AG26 10=>AH27 13=>AG25 14=>AH26 15=>AH24 16=>AF25 17=>AG23 18=>AF23 19=>AG24 20=>AH22 21=>AH21 22=>AG21 23=>AH23 24=>AA20 25=>AF22 26=>AE22 27=>AG20 28=>AF21 31=>AG19 32=>AH19 33=>AG18 34=>AH18 35=>AF18 36=>AF20 37=>AG15 38=>AE20 39=>AE19 40=>AE17), (connector arduino 0 1=>AG13 2=>AF13 3=>AG10 4=>AG9 5=>U14 6=>U13 7=>AG8 8=>AH8 9=>AF17 10=>AE15 11=>AF15 12=>AG16 13=>AH11 14=>AH12 15=>AH9 16=>AG11 17=>AH7)]

toolchain_program(products: BuildProducts, name: str) → None

Extract bitstream for fragment name from products and download it to a target.

class torii_boards.altera.mister.MisterPlatform(*, toolchain: Literal['Quartus', 'Mistral'] = 'Quartus')

device = '5CSEBA6'

package = 'U23'

speed = 'I7'

default_clk = 'clk50'

pretty_name = 'MiSTer FPGA'

description = 'terasIC DE10-Nano based MiSTer FPGA Platform'

resources = [(resource clk50 0 (pins i V11) (clock 50000000.0) (attrs io_standard='3.3-V LVTTL')), (resource clk50 1 (pins i Y13) (clock 50000000.0) (attrs io_standard='3.3-V LVTTL')), (resource clk50 2 (pins i E11) (clock 50000000.0) (attrs io_standard='3.3-V LVTTL')), (resource led 0 (pins o W15) (attrs io_standard='3.3-V LVTTL')), (resource led 1 (pins o AA24) (attrs io_standard='3.3-V LVTTL')), (resource led 2 (pins o V16) (attrs io_standard='3.3-V LVTTL')), (resource led 3 (pins o V15) (attrs io_standard='3.3-V LVTTL')), (resource led 4 (pins o AF26) (attrs io_standard='3.3-V LVTTL')), (resource led 5 (pins o AE26) (attrs io_standard='3.3-V LVTTL')), (resource led 6 (pins o Y16) (attrs io_standard='3.3-V LVTTL')), (resource led 7 (pins o AA23) (attrs io_standard='3.3-V LVTTL')), (resource button 0 (pins-n i AH17) (attrs io_standard='3.3-V LVTTL')), (resource button 1 (pins-n i AH16) (attrs io_standard='3.3-V LVTTL')), (resource switch 0 (pins i Y24) (attrs io_standard='3.3-V LVTTL')), (resource switch 1 (pins i W24) (attrs io_standard='3.3-V LVTTL')), (resource switch 2 (pins i W21) (attrs io_standard='3.3-V LVTTL')), (resource switch 3 (pins i W20) (attrs io_standard='3.3-V LVTTL')), (resource uart 0 (subsignal rx (pins i AG13)) (subsignal tx (pins o AF13)) (attrs io_standard='3.3-V LVTTL')), (resource spi 0 (subsignal cs (pins-n o U9)) (subsignal clk (pins o V10)) (subsignal copi (pins o AC4)) (subsignal cipo (pins i AD4)) (attrs io_standard='3.3-V LVTTL')), (resource adv7513 0 (subsignal tx_d_r (pins o AD12 AE12 W8 Y8 AD11 AD10 AE11 Y5)) (subsignal tx_d_g (pins o AF10 Y4 AE9 AB4 AE7 AF6 AF8 AF5)) (subsignal tx_d_b (pins o AE4 AH2 AH4 AH5 AH6 AG6 AF9 AE8)) (subsignal tx_clk (pins o AG5)) (subsignal tx_de (pins o AD19)) (subsignal tx_hs (pins o T8)) (subsignal tx_vs (pins o V13)) (subsignal tx_int (pins i AF11)) (subsignal i2s0 (pins o T13)) (subsignal mclk (pins o U11)) (subsignal lrclk (pins o T11)) (subsignal sclk (pins o T12)) (subsignal scl (pins io U10)) (subsignal sda (pins io AA4)) (attrs io_standard='3.3-V LVTTL')), (resource sdram 0 (subsignal clk (pins o gpio_0:20)) (subsignal cs (pins-n o gpio_0:33)) (subsignal we (pins-n o gpio_0:27)) (subsignal ras (pins-n o gpio_0:32)) (subsignal cas (pins-n o gpio_0:31)) (subsignal ba (pins o gpio_0:34 gpio_0:35)) (subsignal a (pins o gpio_0:37 gpio_0:38 gpio_0:39 gpio_0:40 gpio_0:28 gpio_0:25 gpio_0:26 gpio_0:23 gpio_0:24 gpio_0:21 gpio_0:36 gpio_0:22 gpio_0:19)) (subsignal dq (pins io gpio_0:1 gpio_0:2 gpio_0:3 gpio_0:4 gpio_0:5 gpio_0:6 gpio_0:7 gpio_0:8 gpio_0:18 gpio_0:17 gpio_0:16 gpio_0:15 gpio_0:14 gpio_0:13 gpio_0:9 gpio_0:10)) (subsignal dqm (pins o )) (attrs io_standard='3.3-V LVCMOS')), (resource power_led 0 (pins-n o gpio_1:1) (attrs io_standard='3.3-V LVTTL')), (resource disk_led 0 (pins-n o gpio_1:3) (attrs io_standard='3.3-V LVTTL')), (resource user_led 0 (pins-n o gpio_1:5) (attrs io_standard='3.3-V LVTTL')), (resource reset_switch 0 (pins-n i gpio_1:17) (attrs io_standard='3.3-V LVTTL')), (resource osd_switch 0 (pins-n i gpio_1:13) (attrs io_standard='3.3-V LVTTL')), (resource user_switch 0 (pins-n i gpio_1:15) (attrs io_standard='3.3-V LVTTL')), (resource audio 0 (subsignal l (pins o gpio_1:2)) (subsignal r (pins o gpio_1:7)) (attrs io_standard='3.3-V LVTTL')), (resource toslink 0 (pins o gpio_1:9)), (resource sd_card_1bit 0 (subsignal clk (pins o gpio_1:13)) (subsignal cmd (pins o gpio_1:8)) (subsignal dat (pins io gpio_1:16)) (subsignal ecd (pins i gpio_1:6)) (attrs io_standard='3.3-V LVTTL')), (resource sd_card_4bit 0 (subsignal clk (pins o gpio_1:13)) (subsignal cmd (pins o gpio_1:8)) (subsignal dat (pins io gpio_1:16 gpio_1:18 gpio_1:4 gpio_1:6)) (attrs io_standard='3.3-V LVTTL')), (resource sd_card_spi 0 (subsignal cs (pins-n io gpio_1:6)) (subsignal clk (pins o gpio_1:13)) (subsignal copi (pins o gpio_1:8)) (subsignal cipo (pins i gpio_1:16)) (attrs io_standard='3.3-V LVTTL')), (resource vga 0 (subsignal r (pins o gpio_1:28 gpio_1:32 gpio_1:34 gpio_1:36 gpio_1:38 gpio_1:40)) (subsignal g (pins o gpio_1:27 gpio_1:31 gpio_1:33 gpio_1:35 gpio_1:37 gpio_1:39)) (subsignal b (pins o gpio_1:21 gpio_1:23 gpio_1:25 gpio_1:26 gpio_1:24 gpio_1:24)) (subsignal hs (pins o gpio_1:20)) (subsignal vs (pins o gpio_1:19)) (attrs io_standard='3.3-V LVTTL'))]

connectors = [(connector gpio 0 1=>V12 2=>E8 3=>W12 4=>D11 5=>D8 6=>AH13 7=>AF7 8=>AH14 9=>AF4 10=>AH3 13=>AD5 14=>AG14 15=>AE23 16=>AE6 17=>AD23 18=>AE24 19=>D12 20=>AD20 21=>C12 22=>AD17 23=>AC23 24=>AC22 25=>Y19 26=>AB23 27=>AA19 28=>W11 31=>AA18 32=>W14 33=>Y18 34=>Y17 35=>AB25 36=>AB26 37=>Y11 38=>AA26 39=>AA13 40=>AA11), (connector gpio 1 1=>Y15 2=>AC24 3=>AA15 4=>AD26 5=>AG28 6=>AF28 7=>AE25 8=>AF27 9=>AG26 10=>AH27 13=>AG25 14=>AH26 15=>AH24 16=>AF25 17=>AG23 18=>AF23 19=>AG24 20=>AH22 21=>AH21 22=>AG21 23=>AH23 24=>AA20 25=>AF22 26=>AE22 27=>AG20 28=>AF21 31=>AG19 32=>AH19 33=>AG18 34=>AH18 35=>AF18 36=>AF20 37=>AG15 38=>AE20 39=>AE19 40=>AE17), (connector arduino 0 1=>AG13 2=>AF13 3=>AG10 4=>AG9 5=>U14 6=>U13 7=>AG8 8=>AH8 9=>AF17 10=>AE15 11=>AF15 12=>AG16 13=>AH11 14=>AH12 15=>AH9 16=>AG11 17=>AH7)]

toolchain_program(products: BuildProducts, name: str) → None

Extract bitstream for fragment name from products and download it to a target.

class torii_boards.altera.rz_easyfpga_a2_2.RZEasyFPGAA2_2Platform(*, toolchain: Literal['Quartus', 'Mistral'] = 'Quartus')

device = 'EP4CE6'

package = 'E22'

speed = 'C8'

default_clk = 'clk50'

default_rst = 'rst'

pretty_name = 'RZ-EasyFPGA A2.2'

description = 'RZ-EasyFPGA Altera Cyclone IV Development Board'

resources = [(resource clk50 0 (pins i 23) (clock 50000000.0) (attrs io_standard='3.3-V LVTTL')), (resource rst 0 (pins-n i 25) (attrs io_standard='3.3-V LVTTL')), (resource led 0 (pins-n o 87) (attrs io_standard='3.3-V LVTTL')), (resource led 1 (pins-n o 86) (attrs io_standard='3.3-V LVTTL')), (resource led 2 (pins-n o 85) (attrs io_standard='3.3-V LVTTL')), (resource led 3 (pins-n o 84) (attrs io_standard='3.3-V LVTTL')), (resource button 0 (pins-n i 88) (attrs io_standard='3.3-V LVTTL')), (resource button 1 (pins-n i 89) (attrs io_standard='3.3-V LVTTL')), (resource button 2 (pins-n i 90) (attrs io_standard='3.3-V LVTTL')), (resource button 3 (pins-n i 91) (attrs io_standard='3.3-V LVTTL')), (resource sdram 0 (subsignal clk (pins o 43)) (subsignal cs (pins-n o 72)) (subsignal we (pins-n o 69)) (subsignal ras (pins-n o 71)) (subsignal cas (pins-n o 70)) (subsignal ba (pins o 73 74)) (subsignal a (pins o 76 77 80 83 68 67 66 65 64 60 75 59)) (subsignal dq (pins io 28 30 31 32 33 34 38 39 54 53 52 51 50 49 46 44)) (subsignal dqm (pins o 42 55)) (attrs io_standard='3.3-V LVCMOS')), (resource vga 0 (subsignal r (pins o 106)) (subsignal g (pins o 105)) (subsignal b (pins o 104)) (subsignal hs (pins o 101)) (subsignal vs (pins o 103))), (resource display_7seg 0 (subsignal a (pins-n o 128)) (subsignal b (pins-n o 121)) (subsignal c (pins-n o 125)) (subsignal d (pins-n o 129)) (subsignal e (pins-n o 132)) (subsignal f (pins-n o 126)) (subsignal g (pins-n o 124)) (subsignal dp (pins-n o 127))), (resource display_7seg_ctrl 0 (subsignal en (pins-n o 133 135 136 137))), (resource ps2 0 (subsignal clk (pins i 119)) (subsignal dat (pins io 120))), (resource i2c 0 (subsignal scl (pins io 112)) (subsignal sda (pins io 113))), (resource i2c 1 (subsignal scl (pins io 99)) (subsignal sda (pins io 98))), (resource buzzer 0 (pins-n o 110)), (resource uart 0 (subsignal rx (pins i 115)) (subsignal tx (pins o 114))), (resource lcd_hd44780 0 (subsignal rs (pins o 141)) (subsignal rw (pins o 138)) (subsignal e (pins o 143)) (subsignal d (pins io 142 1 144 3 2 10 7 11))), (resource cir 0 (subsignal rx (pins i 100)))]

connectors = [(connector gpio 0 3=>11 4=>7 5=>2 6=>144 7=>142 8=>138 9=>136 10=>133 11=>129 12=>127 13=>125 14=>121 15=>119 16=>114 17=>112 18=>110 22=>24 23=>10 24=>3 25=>1 26=>143 27=>141 28=>137 29=>135 30=>132 31=>128 32=>126 33=>124 34=>120 35=>115 36=>113 37=>111), (connector gpio 1 3=>106 4=>105104 5=>103101 6=>10099 7=>98 8=>91 9=>90 10=>89 11=>88 12=>87 13=>86 14=>85 15=>84), (connector gpio 2 1=>30 2=>32 3=>34 4=>39 5=>43 6=>46 7=>50 8=>52 9=>54 10=>58 11=>60 12=>65 13=>67 14=>71 15=>73 16=>75 17=>77 18=>83 22=>28 23=>31 24=>33 25=>38 26=>42 27=>44 28=>51 29=>53 30=>55 31=>59 32=>64 33=>66 34=>68 35=>70 36=>72 37=>74 38=>76 39=>80)]

toolchain_prepare(fragment: Fragment, name: str, **kwargs)

Convert the fragment and constraints recorded in this Platform into a BuildPlan.

toolchain_program(products: BuildProducts, name: str) → None

Extract bitstream for fragment name from products and download it to a target.