Xilinx Board

The torii.platform.vendor.xilinx module provides a base platform to support Xilinx devices with the ISE, Vivado, and Symbiflow toolchains.

class torii_boards.xilinx.alchitry_au.AlchitryAuPlatform(*, toolchain: Literal['Vivado', 'ISE', 'Symbiflow'] | None = None)

device = 'XC7A35T'

package = 'FTG256'

speed = '1'

default_clk = 'clk100'

pretty_name = 'Alchitry Au'

description = 'Alchitry Au Xilinx Artix7 Development Board'

resources = [(resource clk100 0 (pins i N14) (clock 100000000.0) (attrs IOSTANDARD='LVCMOS33')), (resource led 0 (pins o K13) (attrs IOSTANDARD='LVCMOS33')), (resource led 1 (pins o K12) (attrs IOSTANDARD='LVCMOS33')), (resource led 2 (pins o L14) (attrs IOSTANDARD='LVCMOS33')), (resource led 3 (pins o L13) (attrs IOSTANDARD='LVCMOS33')), (resource led 4 (pins o M16) (attrs IOSTANDARD='LVCMOS33')), (resource led 5 (pins o M14) (attrs IOSTANDARD='LVCMOS33')), (resource led 6 (pins o M12) (attrs IOSTANDARD='LVCMOS33')), (resource led 7 (pins o N16) (attrs IOSTANDARD='LVCMOS33')), (resource usb 0 (subsignal usb_tx (pins o P16)) (subsignal usb_rx (pins i P15)) (attrs IOSTANDARD='LVCMOS33')), (resource ddr3 0 (subsignal rst (pins-n o D13)) (subsignal clk (diffpairs o (p G14) (n F14)) (attrs IOSTANDARD='LVDS')) (subsignal clk_en (pins o D15)) (subsignal cs (pins-n o D16)) (subsignal we (pins-n o E11)) (subsignal ras (pins-n o D14)) (subsignal cas (pins-n o D14)) (subsignal a (pins o F12 G16 G15 E16 H11 G12 H16 H12 H16 H13 E12 H14 F13 J15)) (subsignal ba (pins o E13 F15 E15)) (subsignal dqs (diffpairs io (p B15 A15) (n B9 A10)) (attrs IOSTANDARD='LVDS')) (subsignal dq (pins io A13 B16 B14 C11 C13 C16 C12 C14 D8 B11 C8 B10 A12 A8 B12 A9)) (subsignal dm (pins o A14 C9)) (subsignal odt (pins o G11)) (attrs IOSTANDARD='LVCMOS15'))]

connectors = [(connector bank 0 1=>T8 2=>T7 3=>T5 4=>R5 5=>R8 6=>P8 7=>L2 8=>L3 9=>J1 10=>K1 11=>H1 12=>H2 13=>G1 14=>G2 15=>K5 16=>E6 17=>T10 18=>T9 19=>R6 20=>R7 21=>P9 22=>N9 23=>K2 24=>K3 25=>J4 26=>J5 27=>H3 28=>J3 29=>H4 30=>H5 31=>N6 32=>M6), (connector bank 1 1=>D1 2=>E2 3=>A2 4=>B2 5=>E1 6=>F2 7=>F3 8=>F4 9=>A3 10=>B4 11=>A4 12=>A5 13=>B5 14=>B6 15=>A7 16=>B7 17=>B1 18=>C1 19=>C2 20=>C3 21=>D3 22=>E3 23=>C4 24=>D4 25=>G4 26=>G5 27=>E5 28=>F5 29=>D5 30=>D6 31=>C6 32=>C7), (connector bank 2 1=>T13 2=>R13 3=>T12 4=>R12 5=>R11 6=>R10 7=>N2 8=>N3 9=>P3 10=>P4 11=>M4 12=>L4 13=>N4 14=>M5 15=>L5 16=>P5 17=>P11 18=>P10 19=>N12 20=>N11 21=>P13 22=>N13 23=>M1 24=>M2 25=>P1 26=>N1 27=>R1 28=>R2 29=>T2 30=>R3 31=>T3 32=>T4), (connector bank 3 1=>L14 2=>L13 3=>M12 4=>N16 5=>R16 6=>R15 7=>P14 8=>M15 9=>P16 10=>P15 17=>K13 18=>K12 19=>M16 20=>M14 21=>T16 22=>T14 23=>N14)]

toolchain_program(products: BuildProducts, name: str) → None: Extract bitstream for fragment name from products and download it to a target.

class torii_boards.xilinx.arty_a7.ArtyA7_35Platform(*, toolchain: Literal['Vivado', 'ISE', 'Symbiflow'] | None = None)

device = 'xc7a35ti'

pretty_name = 'Arty A7-35T'

description = 'Digilent Arty A7-35T Xilinx Artix7-35 Development Board'

class torii_boards.xilinx.arty_a7.ArtyA7_100Platform(*, toolchain: Literal['Vivado', 'ISE', 'Symbiflow'] | None = None)

device = 'xc7a100ti'

pretty_name = 'Arty A7-100T'

description = 'Digilent Arty-A7-100T Xilinx Artix7-100 Development Board'

class torii_boards.xilinx.arty_s7.ArtyS7_25Platform(*, toolchain: Literal['Vivado', 'ISE', 'Symbiflow'] | None = None)

device = 'xc7s25'

pretty_name = 'Arty S7-25'

description = 'Digilent Arty S7-25 Xilinx Spartan7-25 Development Board'

class torii_boards.xilinx.arty_s7.ArtyS7_50Platform(*, toolchain: Literal['Vivado', 'ISE', 'Symbiflow'] | None = None)

device = 'xc7s50'

pretty_name = 'Arty S7-50'

description = 'Digilent Arty S7-50 Xilinx Spartan7-50 Development Board'

class torii_boards.xilinx.arty_z7.ArtyZ720Platform(*, toolchain: Literal['Vivado', 'ISE', 'Symbiflow'] | None = None)

device = 'xc7z020'

package = 'clg400'

speed = '1'

default_clk = 'clk125'

pretty_name = 'Arty Z7-20'

description = 'Digilent Arty Z7-20 Xilinx Zynq 7020 SoC Development Board'

resources = [(resource clk125 0 (pins i H16) (clock 125000000.0) (attrs IOSTANDARD='LVCMOS33')), (resource switch 0 (pins i M20) (attrs IOSTANDARD='LVCMOS33')), (resource switch 1 (pins i M19) (attrs IOSTANDARD='LVCMOS33')), (resource rgb_led 0 (subsignal r (pins o N15)) (subsignal g (pins o G17)) (subsignal b (pins o L15)) (attrs IOSTANDARD='LVCMOS33')), (resource rgb_led 1 (subsignal r (pins o M15)) (subsignal g (pins o L14)) (subsignal b (pins o G14)) (attrs IOSTANDARD='LVCMOS33')), (resource led 0 (pins o R14) (attrs IOSTANDARD='LVCMOS33')), (resource led 1 (pins o P14) (attrs IOSTANDARD='LVCMOS33')), (resource led 2 (pins o N16) (attrs IOSTANDARD='LVCMOS33')), (resource led 3 (pins o M14) (attrs IOSTANDARD='LVCMOS33')), (resource button 0 (pins i D19) (attrs IOSTANDARD='LVCMOS33')), (resource button 1 (pins i D20) (attrs IOSTANDARD='LVCMOS33')), (resource button 2 (pins i L20) (attrs IOSTANDARD='LVCMOS33')), (resource button 3 (pins i L19) (attrs IOSTANDARD='LVCMOS33')), (resource audio 0 (subsignal pwm (pins o R18)) (subsignal sd (pins-n o T17)) (attrs IOSTANDARD='LVCMOS33')), (resource crypto_sda 0 (pins io J15) (attrs IOSTANDARD='LVCMOS33')), (resource hdmi_rx 0 (subsignal cec (pins io H17)) (subsignal clk (diffpairs i (p N18) (n P19)) (attrs IOSTANDARD='TMDS_33')) (subsignal d (diffpairs i (p V20 T20 N20) (n W20 U20 P20)) (attrs IOSTANDARD='TMDS_33')) (subsignal hpd (pins o T19)) (subsignal scl (pins io U14)) (subsignal sda (pins io U15)) (attrs IOSTANDARD='LVCMOS33')), (resource hdmi_tx 0 (subsignal cec (pins io G15)) (subsignal clk (diffpairs o (p L16) (n L17)) (attrs IOSTANDARD='TMDS_33')) (subsignal d (diffpairs o (p K17 K19 J18) (n K18 J19 H18)) (attrs IOSTANDARD='TMDS_33')) (subsignal hpd (pins-n i R19)) (subsignal scl (pins io M17)) (subsignal sda (pins io M18)) (attrs IOSTANDARD='LVCMOS33'))]

connectors = [(connector pmod 0 1=>Y18 2=>Y19 3=>Y16 4=>Y17 7=>U18 8=>U19 9=>W18 10=>W19), (connector pmod 1 1=>W14 2=>Y14 3=>T11 4=>T10 7=>V16 8=>W16 9=>V12 10=>W13), (connector ck_io 0 io0=>T14 io1=>U12 io2=>U13 io3=>V13 io4=>V15 io5=>T15 io6=>R16 io7=>U17 io8=>V17 io9=>V18 io10=>T16 io11=>R17 io12=>P18 io13=>N17 io26=>U5 io27=>V5 io28=>V6 io29=>U7 io30=>V7 io31=>U8 io32=>V8 io33=>V10 io34=>W10 io35=>W6 io36=>Y6 io37=>Y7 io38=>W8 io39=>Y8 io40=>W9 io41=>Y9 a0=>Y11 a1=>Y12 a2=>W11 a3=>V11 a4=>T5 a5=>U10 a6=>F19 a7=>F20 a8=>C20 a9=>B20 a10=>B19 a11=>A20 a=>Y13), (connector ck_spi 0 cipo=>W15 copi=>T12 sck=>H15 ss=>F16), (connector ck_i2c 0 scl=>P16 sda=>P15), (connector xadc 0 vaux1_n=>D18 vaux1_p=>E17 vaux9_n=>E19 vaux9_p=>E18 vaux6_n=>J14 vaux6_p=>K14 vaux15_n=>J16 vaux15_p=>K16 vaux5_n=>H20 vaux5_p=>J20 vaux13_n=>G20 vaux13_p=>G19 vaux12_n=>F20 vaux12_p=>F19 vaux0_n=>B20 vaux0_p=>C20 vaux8_n=>A20 vaux8_p=>B19)]

toolchain_program(products: BuildProducts, name: str, **kwargs) → None: Extract bitstream for fragment name from products and download it to a target.

class torii_boards.xilinx.atlys.AtlysPlatform(*, JP12: Literal['2V5', '3V3'] = '2V5', **kwargs)

Platform file for Digilent Atlys Spartan 6 board. https://reference.digilentinc.com/reference/programmable-logic/atlys/start

device = 'xc6slx45'

package = 'csg324'

speed = '3'

pretty_name = 'Atlys'

description = 'Digilent Atlys Xilinx Spartan 6 Trainer Board'

bank2_iostandard() → str

default_clk = 'clk100'

default_rst = 'rst'

resources = [(resource rst 0 (pins-n i T15) (attrs IOSTANDARD=<function AtlysPlatform.bank2_iostandard>)), (resource clk100 0 (pins i L15) (clock 100000000.0) (attrs IOSTANDARD='LVCMOS33')), (resource led 0 (pins o U18) (attrs IOSTANDARD='LVCMOS33')), (resource led 1 (pins o M14) (attrs IOSTANDARD='LVCMOS33')), (resource led 2 (pins o N14) (attrs IOSTANDARD='LVCMOS33')), (resource led 3 (pins o L14) (attrs IOSTANDARD='LVCMOS33')), (resource led 4 (pins o M13) (attrs IOSTANDARD='LVCMOS33')), (resource led 5 (pins o D4) (attrs IOSTANDARD='LVCMOS33')), (resource led 6 (pins o P16) (attrs IOSTANDARD='LVCMOS33')), (resource led 7 (pins o N12) (attrs IOSTANDARD=<function AtlysPlatform.bank2_iostandard>)), (resource button 0 (pins i N4) (attrs IOSTANDARD='LVCMOS18')), (resource button 1 (pins i P4) (attrs IOSTANDARD='LVCMOS18')), (resource button 2 (pins i P3) (attrs IOSTANDARD='LVCMOS18')), (resource button 3 (pins i F6) (attrs IOSTANDARD='LVCMOS18')), (resource button 4 (pins i F5) (attrs IOSTANDARD='LVCMOS18')), (resource switch 0 (pins i A10) (attrs IOSTANDARD='LVCMOS33')), (resource switch 1 (pins i D14) (attrs IOSTANDARD='LVCMOS33')), (resource switch 2 (pins i C14) (attrs IOSTANDARD='LVCMOS33')), (resource switch 3 (pins i P15) (attrs IOSTANDARD='LVCMOS33')), (resource switch 4 (pins i P12) (attrs IOSTANDARD=<function AtlysPlatform.bank2_iostandard>)), (resource switch 5 (pins i R5) (attrs IOSTANDARD=<function AtlysPlatform.bank2_iostandard>)), (resource switch 6 (pins i T5) (attrs IOSTANDARD=<function AtlysPlatform.bank2_iostandard>)), (resource switch 7 (pins i E4) (attrs IOSTANDARD='LVCMOS18')), (resource uart 0 (subsignal rx (pins i A16)) (subsignal tx (pins o B16)) (attrs IOSTANDARD='LVCMOS33')), (resource ps2 0 (subsignal clk (pins i P17)) (subsignal dat (pins io N15)) (attrs IOSTANDARD='LVCMOS33')), (resource ps2 1 (subsignal clk (pins i N18)) (subsignal dat (pins io P18)) (attrs IOSTANDARD='LVCMOS33')), (resource spi_flash_1x 0 (subsignal cs (pins-n o AE14)) (subsignal clk (pins o AH18)) (subsignal copi (pins o AF14)) (subsignal cipo (pins i AF20)) (subsignal wp (pins-n o AG21)) (subsignal hold (pins-n o AG17)) (attrs IOSTANDARD='LVCMOS25' SLEW='FAST')), (resource spi_flash_2x 0 (subsignal cs (pins-n o AE14)) (subsignal clk (pins o AH18)) (subsignal dq (pins io AF14 AF20)) (attrs IOSTANDARD='LVCMOS25' SLEW='FAST')), (resource spi_flash_4x 0 (subsignal cs (pins-n o AE14)) (subsignal clk (pins o AH18)) (subsignal dq (pins io AF14 AF20 AG21 AG17)) (attrs IOSTANDARD='LVCMOS25' SLEW='FAST')), (resource ddr2 0 (subsignal clk (diffpairs o (p G3) (n G1)) (attrs IOSTANDARD='DIFF_SSTL18_II' IN_TERM='NONE')) (subsignal clk_en (pins o H7)) (subsignal we (pins-n o E3)) (subsignal ras (pins-n o L5)) (subsignal cas (pins-n o K5)) (subsignal a (pins o J7 J6 H5 L7 F3 H4 H3 H6 D2 D1 F4 D3 G6)) (subsignal ba (pins o F2 F1 E1)) (subsignal dqs (diffpairs o (p P2 L4) (n P1 L3)) (attrs IOSTANDARD='DIFF_SSTL18_II')) (subsignal dq (pins io L2 L1 K2 K1 H2 H1 J3 J1 M3 M1 N2 N1 T2 T1 U2 U1)) (subsignal dm (pins o K4 K3)) (subsignal odt (pins o K6)) (attrs IOSTANDARD='SSTL18_II' SLEW='FAST')), (resource eth_gmii 0 (subsignal rst (pins-n o G13)) (subsignal int (pins-n o L16)) (subsignal mdio (pins io N17)) (subsignal mdc (pins o F16)) (subsignal gtx_clk (pins o L12)) (subsignal tx_clk (pins i K16)) (subsignal tx_en (pins o H15)) (subsignal tx_er (pins o G18)) (subsignal tx_data (pins o H16 H13 K14 K13 J13 G14 H12 K12)) (subsignal rx_clk (pins i K15)) (subsignal rx_dv (pins i F17) (attrs PULLDOWN='TRUE')) (subsignal rx_er (pins i F18)) (subsignal rx_data (pins i G16 H14 E16 F15 F14 E18 D16 D17)) (subsignal col (pins i C17)) (subsignal crs (pins i C18)) (attrs IOSTANDARD='LVCMOS33')), (resource eth_rgmii 0 (subsignal rst (pins-n o G13)) (subsignal int (pins-n o L16)) (subsignal mdio (pins io N17)) (subsignal mdc (pins o F16)) (subsignal tx_clk (pins o L12)) (subsignal tx_ctl (pins o H15)) (subsignal tx_data (pins o H16 H13 K14 K13)) (subsignal rx_clk (pins i K15)) (subsignal rx_ctl (pins i F17) (attrs PULLDOWN='TRUE')) (subsignal rx_data (pins i G16 H14 E16 F15)) (attrs IOSTANDARD='LVCMOS33')), (resource eth_mii 0 (subsignal rst (pins-n o G13)) (subsignal int (pins-n o L16)) (subsignal mdio (pins io N17)) (subsignal mdc (pins o F16)) (subsignal tx_clk (pins i K16)) (subsignal tx_en (pins o H15)) (subsignal tx_er (pins o G18)) (subsignal tx_data (pins o H16 H13 K14 K13)) (subsignal rx_clk (pins i K15)) (subsignal rx_dv (pins i F17) (attrs PULLDOWN='TRUE')) (subsignal rx_er (pins i F18)) (subsignal rx_data (pins i G16 H14 E16 F15)) (subsignal col (pins i C17)) (subsignal crs (pins i C18)) (attrs IOSTANDARD='LVCMOS33')), (resource eth_tbi 0 (subsignal rst (pins-n o G13)) (subsignal int (pins-n o L16)) (subsignal mdio (pins io N17)) (subsignal mdc (pins o F16)) (subsignal tx_clk (pins o L12)) (subsignal tx_data (pins o H16 H13 K14 K13 J13 G14 H12 K12 H15 G18)) (subsignal rx_clk (pins i K15 L12)) (subsignal rx_data (pins i G16 H14 E16 F15 F14 E18 D16 D17 F17 F18)) (subsignal lpbk (pins o C17) (attrs PULLDOWN='TRUE')) (subsignal comma (pins i C18)) (attrs IOSTANDARD='LVCMOS33')), (resource eth_rtbi 0 (subsignal rst (pins-n o G13)) (subsignal int (pins-n o L16)) (subsignal mdio (pins io N17)) (subsignal mdc (pins o F16)) (subsignal tx_clk (pins o L12)) (subsignal tx_data (pins o H16 H13 K14 K13 H15)) (subsignal rx_clk (pins i K15)) (subsignal rx_data (pins i G16 H14 E16 F15 F17)) (attrs IOSTANDARD='LVCMOS33')), (resource hdmi 0 (subsignal scl (pins io C13) (attrs IOSTANDARD='I2C')) (subsignal sda (pins io A13) (attrs IOSTANDARD='I2C')) (subsignal clk (diffpairs i (p D11) (n C11))) (subsignal d (diffpairs i (p G9 B11 B12) (n F9 A11 A12))) (attrs IOSTANDARD='TMDS_33')), (resource hdmi 1 (subsignal scl (pins io D9) (attrs IOSTANDARD='I2C')) (subsignal sda (pins io C9) (attrs IOSTANDARD='I2C')) (subsignal clk (diffpairs o (p B6) (n A6))) (subsignal d (diffpairs o (p D8 C7 B8) (n C8 A7 A8))) (attrs IOSTANDARD='TMDS_33')), (resource hdmi 2 (subsignal scl (pins io M16) (attrs IOSTANDARD='I2C')) (subsignal sda (pins io M18) (attrs IOSTANDARD='I2C')) (subsignal clk (diffpairs i (p H17) (n H18))) (subsignal d (diffpairs i (p K17 L17 J16) (n K18 L18 J18))) (attrs IOSTANDARD='TMDS_33')), (resource hdmi 3 (subsignal scl (pins io C13) (attrs IOSTANDARD='I2C')) (subsignal sda (pins io A13) (attrs IOSTANDARD='I2C')) (subsignal clk (diffpairs io (p T9) (n V9))) (subsignal d (diffpairs io (p R3 T4 N5) (n T3 V4 P6))) (attrs IOSTANDARD='TMDS_33')), (resource ac97 0 (subsignal clk (pins o L13)) (subsignal sync (pins o U17)) (subsignal reset (pins o T17)) (subsignal sdo (pins o N18)) (subsignal sdi (pins i T18)) (attrs IOSTANDARD='LVCMOS33'))]

connectors = [(connector pmod 0 1=>T3 2=>R3 3=>P6 4=>N5 7=>V9 8=>T9 9=>V4 10=>T4), (connector vhdci 0 1=>U16 3=>U15 4=>U13 6=>M11 7=>R11 9=>T12 10=>N10 12=>M10 13=>U11 15=>R10 20=>U10 22=>R8 23=>M8 25=>U8 26=>U7 28=>N7 29=>T6 31=>R7 32=>N6 34=>U5 35=>V16 37=>V15 38=>V13 40=>N11 41=>T11 43=>V12 44=>P11 46=>N9 47=>V11 49=>T10 54=>V10 56=>T8 57=>N8 59=>V8 60=>V7 62=>P8 63=>V6 65=>T7 66=>P7 68=>V5)]

toolchain_program(products: BuildProducts, name: str) → None: Extract bitstream for fragment name from products and download it to a target.

class torii_boards.xilinx.ebaz4205.EBAZ4205Platform(*, toolchain: Literal['Vivado', 'ISE', 'Symbiflow'] | None = None)

device = 'xc7z010'

package = 'clg400'

speed = '1'

default_clk = 'clk33_333'

pretty_name = 'EBAZ4205'

description = 'EBAZ4205 Ebit E9+ Xilinx Zynq-7010 Board'

resources = [(resource clk33_333 0 (pins i N18) (clock 33333000.0) (attrs IOSTANDARD='LVCMOS33')), (resource led 0 (pins o W14) (attrs IOSTANDARD='LVCMOS33')), (resource led 1 (pins o W13) (attrs IOSTANDARD='LVCMOS33')), (resource uart 0 (subsignal rx (pins i B19)) (subsignal tx (pins o B20)) (attrs IOSTANDARD='LVCMOS33'))]

connectors = []

toolchain_program(products: BuildProducts, name: str, **kwargs) → None: Extract bitstream for fragment name from products and download it to a target.

class torii_boards.xilinx.genesys2.Genesys2Platform(JP6: Literal['1V2', '1V8', '2V5', '3V3'] = '2V5')

Platform file for Diglient Genesys2 Kitex-7 board. https://reference.digilentinc.com/reference/programmable-logic/genesys-2/start

device = 'xc7k325t'

package = 'ffg900'

speed = '2'

pretty_name = 'Gensys 2'

description = 'Digilent Gensys 2 Xilinx Kintex7-325T Development Board'

bank15_16_17_iostandard() → str

default_rst = 'rst'

default_clk = 'clk'

resources = [(resource rst 0 (pins-n i R19) (attrs IOSTANDARD='LVCMOS33')), (resource clk 0 (diffpairs i (p AD12) (n AD11)) (clock 200000000.0) (attrs IOSTANDARD='LVDS')), (resource button 0 (pins i E18) (attrs IOSTANDARD=<function Genesys2Platform.bank15_16_17_iostandard>)), (resource button 1 (pins i B19) (attrs IOSTANDARD=<function Genesys2Platform.bank15_16_17_iostandard>)), (resource button 2 (pins i C19) (attrs IOSTANDARD=<function Genesys2Platform.bank15_16_17_iostandard>)), (resource button 3 (pins i M19) (attrs IOSTANDARD=<function Genesys2Platform.bank15_16_17_iostandard>)), (resource button 4 (pins i M20) (attrs IOSTANDARD=<function Genesys2Platform.bank15_16_17_iostandard>)), (resource switch 0 (pins i G19) (attrs IOSTANDARD=<function Genesys2Platform.bank15_16_17_iostandard>)), (resource switch 1 (pins i G25) (attrs IOSTANDARD=<function Genesys2Platform.bank15_16_17_iostandard>)), (resource switch 2 (pins i H24) (attrs IOSTANDARD=<function Genesys2Platform.bank15_16_17_iostandard>)), (resource switch 3 (pins i K19) (attrs IOSTANDARD=<function Genesys2Platform.bank15_16_17_iostandard>)), (resource switch 4 (pins i N19) (attrs IOSTANDARD=<function Genesys2Platform.bank15_16_17_iostandard>)), (resource switch 5 (pins i P19) (attrs IOSTANDARD=<function Genesys2Platform.bank15_16_17_iostandard>)), (resource switch 6 (pins i P26) (attrs IOSTANDARD='LVCMOS33')), (resource switch 7 (pins i P27) (attrs IOSTANDARD='LVCMOS33')), (resource led 0 (pins o T28) (attrs IOSTANDARD='LVCMOS33')), (resource led 1 (pins o V19) (attrs IOSTANDARD='LVCMOS33')), (resource led 2 (pins o U30) (attrs IOSTANDARD='LVCMOS33')), (resource led 3 (pins o U29) (attrs IOSTANDARD='LVCMOS33')), (resource led 4 (pins o V20) (attrs IOSTANDARD='LVCMOS33')), (resource led 5 (pins o V26) (attrs IOSTANDARD='LVCMOS33')), (resource led 6 (pins o W24) (attrs IOSTANDARD='LVCMOS33')), (resource led 7 (pins o W23) (attrs IOSTANDARD='LVCMOS33')), (resource fan 0 (subsignal pwm (pins o W19)) (subsignal tach (pins i V21)) (attrs IOSTANDARD='LVCMOS33')), (resource uart 0 (subsignal rx (pins i Y20)) (subsignal tx (pins o Y23)) (attrs IOSTANDARD='LVCMOS33')), (resource i2c 0 (subsignal scl (pins io AE30)) (subsignal sda (pins io AF30)) (attrs IOSTANDARD='LVCMOS33')), (resource ddr3 0 (subsignal rst (pins-n o AG5) (attrs IOSTANDARD='SSTL15')) (subsignal clk (diffpairs o (p AB9) (n AC9)) (attrs IOSTANDARD='DIFF_SSTL15_DCI')) (subsignal clk_en (pins o AJ9)) (subsignal cs (pins-n o AH12)) (subsignal we (pins-n o AG13)) (subsignal ras (pins-n o AE11)) (subsignal cas (pins-n o AF11)) (subsignal a (pins o AC12 AE8 AD8 AC10 AD9 AA13 AA10 AA11 Y10 Y11 AB8 AA8 AB12 AA12 AH9 AG9)) (subsignal ba (pins o AE9 AB10 AC11)) (subsignal dqs (diffpairs io (p AD2 AG4 AG2 AH7) (n AD1 AG3 AH1 AJ7)) (attrs IOSTANDARD='DIFF_SSTL15_DCI' ODT='RTT_40')) (subsignal dq (pins io AD3 AC2 AC1 AC5 AC4 AD6 AE6 AC7 AF2 AE1 AF1 AE4 AE3 AE5 AF5 AF6 AJ4 AH6 AH5 AH2 AJ2 AJ1 AK1 AJ3 AF7 AG7 AJ6 AK6 AJ8 AK8 AK5 AK4) (attrs ODT='RTT_40')) (subsignal dm (pins o AD4 AF3 AH4 AF8)) (subsignal odt (pins o AK9)) (attrs IOSTANDARD='SSTL15_DCI' SLEW='FAST' OUTPUT_IMPEDANCE='RDRV_40_40')), (resource audio_i2c 0 (subsignal scl (pins io AE19)) (subsignal sda (pins io AF18)) (subsignal adr (pins o AD19 AG19)) (attrs IOSTANDARD='LVCMOS18')), (resource audio_i2s 0 (subsignal clk (pins o AG18)) (subsignal sd_adc (pins o AH19)) (subsignal sd_dac (pins i AJ19)) (subsignal ws (pins o AJ18)) (attrs IOSTANDARD='LVCMOS18')), (resource audio_clk 0 (pins o AK19) (attrs IOSTANDARD='LVCMOS18')), (resource spi 0 (subsignal cs (pins-n o dummy-cs0)) (subsignal clk (pins o AF17)) (subsignal copi (pins o Y15)) (subsignal cipo (pins i dummy-cipo0)) (subsignal reset (pins o AB17)) (attrs IOSTANDARD='LVCMOS18')), (resource oled 0 (subsignal dc (pins o AC17)) (subsignal vdd_en (pins-n o AG17)) (subsignal vbat_en (pins-n o AB22) (attrs IOSTANDARD='LVCMOS33')) (attrs IOSTANDARD='LVCMOS18')), (resource hdmi 0 (subsignal scl (pins io AF27) (attrs IOSTANDARD='LVCMOS33')) (subsignal sda (pins io AF26) (attrs IOSTANDARD='LVCMOS33')) (subsignal clk (diffpairs o (p AA20) (n AB20))) (subsignal d (diffpairs o (p AC20 AA22 AB24) (n AC21 AA23 AC25))) (attrs IOSTANDARD='TMDS_33')), (resource hdmi 1 (subsignal scl (pins io AJ28) (attrs IOSTANDARD='LVCMOS33')) (subsignal sda (pins io AJ29) (attrs IOSTANDARD='LVCMOS33')) (subsignal clk (diffpairs i (p AE28) (n AF28))) (subsignal rx (diffpairs i (p AJ26 AG27 AH26) (n AK26 AG28 AH27))) (attrs IOSTANDARD='TMDS_33')), (resource vga 0 (subsignal r (pins o AK25 AG25 AH25 AK24 AJ24)) (subsignal g (pins o AJ23 AJ22 AH22 AK21 AJ21 AK23)) (subsignal b (pins o AH20 AG20 AF21 AK20 AG22)) (subsignal hs (pins-n o AF20)) (subsignal vs (pins-n o AG23)) (attrs IOSTANDARD='LVCMOS33')), (resource sd_card_1bit 0 (subsignal cd (pins i P28)) (subsignal clk (pins o R28)) (subsignal cmd (pins o R29)) (subsignal dat (pins io R26)) (subsignal ecd (pins i T30)) (attrs IOSTANDARD='LVCMOS33')), (resource sd_card_4bit 0 (subsignal cd (pins i P28)) (subsignal clk (pins o R28)) (subsignal cmd (pins o R29)) (subsignal dat (pins io R26 R30 P29 T30)) (attrs IOSTANDARD='LVCMOS33')), (resource sd_card_spi 0 (subsignal cd (pins i P28)) (subsignal cs (pins-n io T30)) (subsignal clk (pins o R28)) (subsignal copi (pins o R29)) (subsignal cipo (pins i R26)) (attrs IOSTANDARD='LVCMOS33')), (resource sd_card_rst 0 (pins o AE24) (attrs IOSTANDARD='LVCMOS33')), (resource usb 0 (subsignal data (pins io AE14 AE15 AC15 AC16 AB15 AA15 AD14 AC14)) (subsignal clk (pins i AD18) (clock 60000000.0)) (subsignal dir (pins i Y16)) (subsignal nxt (pins i AA16)) (subsignal stp (pins o AA17)) (subsignal rst (pins-n o AB14)) (attrs IOSTANDARD='LVCMOS18')), (resource vusb_oc 0 (pins-n i AF16) (attrs IOSTANDARD='LVCMOS18')), (resource eth_rgmii 0 (subsignal rst (pins-n o AH24) (attrs IOSTANDARD='LVCMOS33')) (subsignal mdc (pins o AF12)) (subsignal mdio (pins io AG12)) (subsignal tx_clk (pins o AE10)) (subsignal tx_ctl (pins o AK14)) (subsignal tx_data (pins o AJ12 AK11 AJ11 AK10)) (subsignal rx_clk (pins i AG10)) (subsignal rx_ctl (pins i AH11)) (subsignal rx_data (pins i AJ14 AH14 AK13 AJ13)) (attrs IOSTANDARD='LVCMOS15'))]

connectors = [(connector pmod 0 1=>U27 2=>U28 3=>T26 4=>T27 7=>T22 8=>T23 9=>T20 10=>T21), (connector pmod 1 1=>V29 2=>V30 3=>V25 4=>W26 7=>T25 8=>U25 9=>U22 10=>U23), (connector pmod 2 1=>AC26 2=>AJ27 3=>AH30 4=>AK29 7=>AD26 8=>AG30 9=>AK30 10=>AK28), (connector pmod 3 1=>V27 2=>Y30 3=>V24 4=>W22 7=>U24 8=>Y26 9=>V22 10=>W21), (connector pmod 4 1=>J23 2=>K23 3=>L22 4=>L21 7=>J24 8=>K24 9=>L23 10=>K21), (connector hpc 0 dp1_m2c_p=>Y6 dp1_m2c_n=>Y5 dp2_m2c_p=>W4 dp2_m2c_n=>W3 dp3_m2c_p=>V6 dp3_m2c_n=>V5 dp1_c2m_p=>V2 dp1_c2m_n=>V1 dp2_c2m_p=>U4 dp2_c2m_n=>U3 dp3_c2m_p=>T2 dp3_c2m_n=>T1 dp0_c2m_p=>Y2 dp0_c2m_n=>Y1 dp0_m2c_p=>AA4 dp0_m2c_n=>AA3 la06_p=>D29 la06_n=>C30 la10_p=>B27 la10_n=>A27 la14_p=>C24 la14_n=>B24 la18_cc_p=>D17 la18_cc_n=>D18 la27_p=>A20 la27_n=>A21 ha01_cc_p=>M28 ha01_cc_n=>L28 ha05_p=>J29 ha05_n=>H29 ha09_p=>L30 ha09_n=>K30 ha13_p=>K26 ha13_n=>J26 ha16_p=>M22 ha16_n=>M23 ha20_p=>G27 ha20_n=>F27 clk1_m2c_p=>E28 clk1_m2c_n=>D28 la00_cc_p=>D27 la00_cc_n=>C27 la03_p=>E29 la03_n=>E30 la08_p=>C29 la08_n=>B29 la12_p=>F26 la12_n=>E26 la16_p=>E23 la16_n=>D23 la20_p=>G22 la20_n=>F22 la22_p=>J17 la22_n=>H17 la25_p=>D22 la25_n=>C22 la29_p=>B18 la29_n=>A18 la31_p=>C17 la31_n=>B17 la33_p=>D16 la33_n=>C16 ha03_p=>N25 ha03_n=>N26 ha07_p=>M29 ha07_n=>M30 ha11_p=>P23 ha11_n=>N24 ha14_p=>N27 ha14_n=>M27 ha18_p=>E19 ha18_n=>D19 ha22_p=>D21 ha22_n=>C21 gbtclk1_m2c_p=>N8 gbtclk1_m2c_n=>N7 gbtclk0_m2c_p=>L8 gbtclk0_m2c_n=>L7 la01_cc_p=>D26 la01_cc_n=>C26 la05_p=>B30 la05_n=>A30 la09_p=>B28 la09_n=>A28 la13_p=>E24 la13_n=>D24 la17_cc_p=>F21 la17_cc_n=>E21 la23_p=>G17 la23_n=>F17 la26_p=>B22 la26_n=>A22 pg_m2c=>AH21 ha00_cc_p=>K28 ha00_cc_n=>K29 ha04_p=>M24 ha04_n=>M25 ha08_p=>J27 ha08_n=>J28 ha12_p=>L26 ha12_n=>L27 ha15_p=>J21 ha15_n=>J22 ha19_p=>G29 ha19_n=>F30 prsnt_m2c_b=>AA21 clk0_m2c_p=>F20 clk0_m2c_n=>E20 la02_p=>H30 la02_n=>G30 la04_p=>H26 la04_n=>H27 la07_p=>F25 la07_n=>E25 la11_p=>A25 la11_n=>A26 la15_p=>B23 la15_n=>A23 la19_p=>H21 la19_n=>H22 la21_p=>L17 la21_n=>L18 la24_p=>H20 la24_n=>G20 la28_p=>J19 la28_n=>H19 la30_p=>A16 la30_n=>A17 la32_p=>K18 la32_n=>J18 ha02_p=>P21 ha02_n=>P22 ha06_p=>N29 ha06_n=>N30 ha10_p=>N21 ha10_n=>N22 ha17_cc_p=>C25 ha17_cc_n=>B25 ha21_p=>G28 ha21_n=>F28 ha23_p=>G18 ha23_n=>F18)]

toolchain_prepare(fragment: Fragment, name: str, **kwargs) → BuildPlan: Convert the fragment and constraints recorded in this Platform into a BuildPlan.

property file_templates: Dict[str, str]

toolchain_program(products: BuildProducts, name: str) → None: Extract bitstream for fragment name from products and download it to a target.

class torii_boards.xilinx.kc705.KC705Platform(*, toolchain: Literal['Vivado', 'ISE', 'Symbiflow'] | None = None)

device = 'xc7k325t'

package = 'ffg900'

speed = '2'

default_clk = 'clk156'

pretty_name = 'KC705'

description = 'Xilinx KC705 Kintex7-325T Evaluation Board'

resources = [(resource clk156 0 (diffpairs i (p K28) (n K29)) (clock 156000000.0) (attrs IOSTANDARD='LVDS_25')), (resource led 0 (pins o AB8) (attrs IOSTANDARD='LVCMOS15')), (resource led 1 (pins o AA8) (attrs IOSTANDARD='LVCMOS15')), (resource led 2 (pins o AC9) (attrs IOSTANDARD='LVCMOS15')), (resource led 3 (pins o AB9) (attrs IOSTANDARD='LVCMOS15')), (resource led 4 (pins o AE26) (attrs IOSTANDARD='LVCMOS15')), (resource led 5 (pins o G19) (attrs IOSTANDARD='LVCMOS15')), (resource led 6 (pins o E18) (attrs IOSTANDARD='LVCMOS15')), (resource led 7 (pins o F16) (attrs IOSTANDARD='LVCMOS15')), (resource uart 0 (subsignal rx (pins i M19)) (subsignal tx (pins o K24)) (attrs IOSTANDARD='LVCMOS33'))]

toolchain_program(products: BuildProducts, name: str) → None: Extract bitstream for fragment name from products and download it to a target.

class torii_boards.xilinx.kcu105.KCU105Platform(*, toolchain: Literal['Vivado', 'ISE', 'Symbiflow'] | None = None)

device = 'xcku040'

package = 'ffva1156'

speed = '2-e'

default_clk = 'clk125'

pretty_name = 'KCU105'

description = 'Xilinx Kintex UltraScale Evaluation Board'

resources = [(resource clk125 0 (diffpairs i (p G10) (n F10)) (clock 125000000.0) (attrs IOSTANDARD='LVDS')), (resource led 0 (pins o AP8) (attrs IOSTANDARD='LVCMOS18')), (resource led 1 (pins o H23) (attrs IOSTANDARD='LVCMOS18')), (resource led 2 (pins o P20) (attrs IOSTANDARD='LVCMOS18')), (resource led 3 (pins o P21) (attrs IOSTANDARD='LVCMOS18')), (resource led 4 (pins o N22) (attrs IOSTANDARD='LVCMOS18')), (resource led 5 (pins o M22) (attrs IOSTANDARD='LVCMOS18')), (resource led 6 (pins o R23) (attrs IOSTANDARD='LVCMOS18')), (resource led 7 (pins o P23) (attrs IOSTANDARD='LVCMOS18'))]

toolchain_program(products: BuildProducts, name: str) → None: Extract bitstream for fragment name from products and download it to a target.

class torii_boards.xilinx.mega65.Mega65r3Platform(*, toolchain: Literal['Vivado', 'ISE', 'Symbiflow'] | None = None)

device = 'xc7a200t'

package = 'fbg484'

speed = '2'

default_clk = 'clk100'

pretty_name = 'Mega65'

description = 'Mega65 Xilinx Artix7-200T Based 8-bit computer'

resources = [(resource clk100 0 (pins i V13) (clock 100000000.0) (attrs IOSTANDARD='LVCMOS33')), (resource led 0 (pins o U22) (attrs IOSTANDARD='LVCMOS33')), (resource iec 0 (subsignal rst (pins o AB21)) (subsignal atn (pins o N17)) (subsignal data_en (pins o Y21)) (subsignal data_o (pins o Y22)) (subsignal data_i (pins i AB22) (attrs PULLUP='TRUE')) (subsignal clk_en (pins o AA21)) (subsignal clk_o (pins o Y19)) (subsignal clk_i (pins i Y18) (attrs PULLUP='TRUE')) (subsignal srq_en (pins o AB20)) (subsignal srq_o (pins o U20)) (subsignal srq_i (pins i AA18)) (attrs IOSTANDARD='LVCMOS33')), (resource cart 0 (subsignal ctrl_en (pins o G18)) (subsignal ctrl_dir (pins o U17)) (subsignal addr_en (pins o L19)) (subsignal addr_dir_lo (pins o L21)) (subsignal addr_dir_hi (pins o L18)) (subsignal data_en (pins o U21)) (subsignal data_dir (pins o V22)) (subsignal phi2 (pins o V17)) (subsignal dotclk (pins o AA19)) (subsignal rst (pins o N14)) (subsignal nmi (pins i W17)) (subsignal irq (pins i P14)) (subsignal dma (pins i P15)) (subsignal exrom (pins io R19)) (subsignal ba (pins io N13)) (subsignal rw (pins io R18)) (subsignal rom_lo (pins io AB18)) (subsignal rom_hi (pins io T18)) (subsignal io1 (pins io N15)) (subsignal game (pins io W22)) (subsignal io2 (pins io AA20)) (subsignal data (pins io P16 R17 P20 R16 U18 V18 W20 W21)) (subsignal addr (pins io K19 K18 K21 M22 L20 J20 J21 K22 H17 H20 G20 J15 H19 M20 N22 H18)) (attrs IOSTANDARD='LVCMOS33')), (resource keyboard 0 (subsignal clk (pins o A14)) (subsignal out (pins o A13)) (subsignal in (pins i C13)) (subsignal tck (pins o E13)) (subsignal tdo (pins o E14)) (subsignal tdi (pins i D15)) (subsignal tms (pins o D14)) (subsignal jtag_en (pins o B13)) (attrs IOSTANDARD='LVCMOS33')), (resource paddle 0 (subsignal in (pins i H13 G15 J14 J22)) (subsignal drain (pins o H22)) (attrs IOSTANDARD='LVCMOS33')), (resource joystick 0 (subsignal up (pins i C14)) (subsignal down (pins i F16)) (subsignal left (pins i F14)) (subsignal right (pins i F13)) (subsignal fire (pins i E17)) (attrs IOSTANDARD='LVCMOS33')), (resource joystick 1 (subsignal up (pins i W19)) (subsignal down (pins i P17)) (subsignal left (pins i F21)) (subsignal right (pins i C15)) (subsignal fire (pins i F15)) (attrs IOSTANDARD='LVCMOS33')), (resource vgadac 0 (subsignal clk (pins o AA9)) (subsignal r (pins o U15 V15 T14 Y17 Y16 AB17 AA16 AB16)) (subsignal g (pins o Y14 W14 AA15 AB15 Y13 AA14 AA13 AB13)) (subsignal b (pins o W10 Y12 AB12 AA11 AB11 Y11 AB10 AA10)) (subsignal hs (pins o W12)) (subsignal vs (pins o V14)) (subsignal sync (pins-n o V10)) (subsignal blank (pins-n o W11)) (attrs IOSTANDARD='LVCMOS33')), (resource hdmi 0 (subsignal clk (diffpairs o (p W1) (n Y1))) (subsignal data (diffpairs o (p AA1 AB3 AA5) (n AB1 AB2 AB5))) (subsignal scl (pins io AB7)) (subsignal sda (pins io V9)) (subsignal en (pins o AB8)) (subsignal hpd (pins i Y8)) (subsignal hpd_en (pins o M15)) (subsignal cec (pins o W9)) (attrs IOSTANDARD='LVCMOS33')), (resource i2c 0 (subsignal scl (pins io A15)) (subsignal sda (pins io A16)) (attrs IOSTANDARD='LVCMOS33')), (resource grove 0 (subsignal scl (pins io G21)) (subsignal sda (pins io G22)) (attrs IOSTANDARD='LVCMOS33')), (resource audio 0 (subsignal left (pins o L6)) (subsignal right (pins o F4)) (subsignal sd (pins o F18)) (subsignal speaker (pins o E16)) (subsignal mclk (pins o D16)) (subsignal bclk (pins o E19)) (subsignal sync (pins o F19)) (attrs IOSTANDARD='LVCMOS33')), (resource spi_flash 0 (subsignal data (pins io P22 R22 P21 R21) (attrs PULLUP='TRUE')) (subsignal cs (pins-n o T19))), (resource hyper_ram 0 (subsignal clk (pins o D22) (attrs SLEW='FAST' DRIVE='16')) (subsignal data (pins io A21 D21 C20 A20 B20 A19 E21 E22) (attrs SLEW='FAST' DRIVE='16')) (subsignal rwds (pins io B21) (attrs SLEW='FAST' DRIVE='16')) (subsignal rst (pins o B22)) (subsignal cs (pins o C22)) (attrs IOSTANDARD='LVCMOS33' PULLUP='FALSE')), (resource ethernet 0 (subsignal led (pins o R14)) (subsignal clk (pins o L4) (attrs SLEW='FAST')) (subsignal rst (pins o K6)) (subsignal mdio (pins io L5)) (subsignal mdc (pins o J6)) (subsignal rxd (pins i P4 L1)) (subsignal txd (pins o L3 K3) (attrs SLEW='SLOW' DRIVE='4')) (subsignal rxer (pins i M6)) (subsignal txen (pins o J4) (attrs SLEW='SLOW' DRIVE='4')) (subsignal rxdv (pins i K4)) (attrs IOSTANDARD='LVCMOS33')), (resource uart 0 (subsignal rx (pins i L14)) (subsignal tx (pins o L13)) (attrs IOSTANDARD='LVCMOS33')), (resource max10 0 (subsignal tx (pins i M13)) (subsignal rx (pins o K16)) (subsignal rst (pins io L16)) (attrs IOSTANDARD='LVCMOS33')), (resource sd_card_1bit 0 (subsignal cd (pins i D17)) (subsignal wp (pins-n i C17)) (subsignal clk (pins o B17)) (subsignal cmd (pins o B16)) (subsignal dat (pins io B18)) (subsignal ecd (pins i B15)) (attrs IOSTANDARD='LVCMOS33')), (resource sd_card_4bit 0 (subsignal cd (pins i D17)) (subsignal wp (pins-n i C17)) (subsignal clk (pins o B17)) (subsignal cmd (pins o B16)) (subsignal dat (pins io B18 C18 C19 B15)) (attrs IOSTANDARD='LVCMOS33')), (resource sd_card_spi 0 (subsignal cd (pins i D17)) (subsignal wp (pins-n i C17)) (subsignal cs (pins-n io B15)) (subsignal clk (pins o B17)) (subsignal copi (pins o B16)) (subsignal cipo (pins i B18)) (attrs IOSTANDARD='LVCMOS33')), (resource sd_card_1bit 1 (subsignal cd (pins i K1)) (subsignal clk (pins o G2)) (subsignal cmd (pins o J2)) (subsignal dat (pins io H2)) (subsignal ecd (pins i K2)) (attrs IOSTANDARD='LVCMOS33')), (resource sd_card_4bit 1 (subsignal cd (pins i K1)) (subsignal clk (pins o G2)) (subsignal cmd (pins o J2)) (subsignal dat (pins io H2 H3 J1 K2)) (attrs IOSTANDARD='LVCMOS33')), (resource sd_card_spi 1 (subsignal cd (pins i K1)) (subsignal cs (pins-n io K2)) (subsignal clk (pins o G2)) (subsignal copi (pins o J2)) (subsignal cipo (pins i H2)) (attrs IOSTANDARD='LVCMOS33')), (resource floppy 0 (subsignal density (pins o P6)) (subsignal motor (pins o M5 H15)) (subsignal select (pins o N5 G17)) (subsignal step_dir (pins o P5)) (subsignal step (pins o M3)) (subsignal wdata (pins o N4)) (subsignal wgate (pins o N3)) (subsignal side1 (pins o M1)) (subsignal index (pins i M2)) (subsignal track0 (pins i N2)) (subsignal wp (pins i P2)) (subsignal rdata (pins i P1)) (subsignal diskchanged (pins i R1)) (attrs IOSTANDARD='LVCMOS33'))]

connectors = [(connector pmod 0 1=>G1 2=>E1 3=>C2 4=>B1 7=>F1 8=>D1 9=>B2 10=>A1), (connector pmod 1 1=>E2 2=>D2 3=>G4 4=>J5 7=>F3 8=>E3 9=>H4 10=>H5), (connector test 0 1=>T16 2=>U16 3=>W16 4=>J19 5=>K17 6=>N19 7=>N20 8=>D20)]

class torii_boards.xilinx.mercury.MercuryPlatform(*, toolchain: Literal['Vivado', 'ISE', 'Symbiflow'] | None = None)

Original Mercury Board from Micro-Nova: https://www.micro-nova.com

Mercury Manual: https://www.micro-nova.com/s/mercury_rm.pdf Mercury Schematic: https://www.micro-nova.com/s/mercury_schematic.pdf

The Mercury board is often paired with an extension board called the Baseboard, which provides an ample set of I/O for FPGA beginners.

Baseboard Manual: https://www.micro-nova.com/s/baseboard_rm.pdf Baseboard Schematics: https://www.micro-nova.com/s/baseboard_schematic.pdf

Mercury and Baseboard Resources: https://www.micro-nova.com/resources-mercury

device = 'xc3s200a'

package = 'vq100'

speed = '4'

default_clk = 'clk50'

pretty_name = 'Micro-Nova Mercury'

description = 'Micro-Nova Mercury Xilinx Spartan-3A based FPGA Module'

resources = [(resource clk50 0 (pins i P43) (clock 50000000.0) (attrs IOSTANDARD='LVCMOS33')), (resource button 0 (pins i P41) (attrs IOSTANDARD='LVTTL')), (resource spi_serial 0 (subsignal cs (pins-n i P39)) (subsignal clk (pins i P53)) (subsignal copi (pins i P46)) (subsignal cipo (pins oe P51)) (attrs IOSTANDARD='LVTTL')), (resource spi_flash_1x 0 (subsignal cs (pins-n o P27)) (subsignal clk (pins o P53)) (subsignal copi (pins o P46)) (subsignal cipo (pins i P51)) (attrs IOSTANDARD='LVTTL')), (resource spi_flash_2x 0 (subsignal cs (pins-n o P27)) (subsignal clk (pins o P53)) (subsignal dq (pins io P46 P51)) (attrs IOSTANDARD='LVTTL')), (resource spi_adc 0 (subsignal cs (pins-n o P12)) (subsignal clk (pins o P9)) (subsignal copi (pins o P10)) (subsignal cipo (pins i P21)) (attrs IOSTANDARD='LVTTL')), (resource bussw_oe 0 (pins-n o P30N) (attrs IOSTANDARD='LVTTL'))]

connectors = [(connector gpio 0 1=>P59 2=>P60 3=>P61 4=>P62 5=>P64 6=>P57 7=>P56 8=>P52 9=>P50 10=>P49 11=>P85 12=>P84 13=>P83 14=>P78 15=>P77 16=>P65 17=>P70 18=>P71 19=>P72 20=>P73 21=>P5 22=>P4 23=>P6 24=>P98 25=>P94 26=>P93 27=>P90 28=>P89 29=>P88 30=>P86), (connector dio 0 1=>P20 2=>P32 3=>P33 4=>P34 5=>P35 6=>P36 7=>P37), (connector clkio 0 1=>P40 2=>P44), (connector input 0 1=>P68 2=>P97 3=>P7 4=>P82), (connector led 0 1=>P13 2=>P15 3=>P16 4=>P19), (connector pmod 0 1=>P5 2=>P4 3=>P6 4=>P98 5=>P94 6=>P93 7=>P90 8=>P89)]

leds = [(resource led 0 (pins o led_0:1) (attrs IOSTANDARD='LVTTL')), (resource led 1 (pins o led_0:2) (attrs IOSTANDARD='LVTTL')), (resource led 2 (pins o led_0:3) (attrs IOSTANDARD='LVTTL')), (resource led 3 (pins o led_0:4) (attrs IOSTANDARD='LVTTL'))]

sram = [(resource sram 0 (subsignal cs (pins-n o P3)) (subsignal we (pins-n o gpio_0:29)) (subsignal a (pins o gpio_0:1 gpio_0:2 gpio_0:3 gpio_0:4 gpio_0:5 gpio_0:6 gpio_0:7 gpio_0:8 gpio_0:9 gpio_0:10 gpio_0:11 gpio_0:12 gpio_0:13 gpio_0:14 gpio_0:15 gpio_0:16 gpio_0:17 gpio_0:18 gpio_0:19)) (subsignal d (pins io gpio_0:21 gpio_0:22 gpio_0:23 gpio_0:24 gpio_0:25 gpio_0:26 gpio_0:27 gpio_0:28)) (attrs IOSTANDARD='LVTTL' SLEW='FAST'))]

serial = [(resource uart 0 (subsignal rx (pins i input_0:1)) (subsignal tx (pins o dio_0:1)) (attrs IOSTANDARD='LVCMOS33'))]

baseboard_sram = [(resource button 1 (pins i input_0:1) (attrs IOSTANDARD='LVTTL')), (resource button 2 (pins i input_0:2) (attrs IOSTANDARD='LVTTL')), (resource button 3 (pins i input_0:3) (attrs IOSTANDARD='LVTTL')), (resource button 4 (pins i input_0:4) (attrs IOSTANDARD='LVTTL')), (resource vga 0 (subsignal r (pins o dio_0:1 dio_0:2 dio_0:3)) (subsignal g (pins o dio_0:4 dio_0:5 dio_0:6)) (subsignal b (pins o dio_0:7 clkio_0:1)) (subsignal hs (pins-n o led_0:3)) (subsignal vs (pins-n o led_0:4)) (attrs IOSTANDARD='LVCMOS33' SLEW='FAST')), (resource extclk 0 (pins i clkio_1:1) (attrs IOSTANDARD='LVCMOS33')), (resource ps2 0 (subsignal clk (pins i led_0:2)) (subsignal dat (pins io led_0:1)) (attrs IOSTANDARD='LVTTL'))]

baseboard_no_sram = [(resource button 1 (pins i input_0:1) (attrs IOSTANDARD='LVTTL')), (resource button 2 (pins i input_0:2) (attrs IOSTANDARD='LVTTL')), (resource button 3 (pins i input_0:3) (attrs IOSTANDARD='LVTTL')), (resource button 4 (pins i input_0:4) (attrs IOSTANDARD='LVTTL')), (resource vga 0 (subsignal r (pins o dio_0:1 dio_0:2 dio_0:3)) (subsignal g (pins o dio_0:4 dio_0:5 dio_0:6)) (subsignal b (pins o dio_0:7 clkio_0:1)) (subsignal hs (pins-n o led_0:3)) (subsignal vs (pins-n o led_0:4)) (attrs IOSTANDARD='LVCMOS33' SLEW='FAST')), (resource extclk 0 (pins i clkio_1:1) (attrs IOSTANDARD='LVCMOS33')), (resource ps2 0 (subsignal clk (pins i led_0:2)) (subsignal dat (pins io led_0:1)) (attrs IOSTANDARD='LVTTL')), (resource switch 0 (pins i gpio_0:1) (attrs IOSTANDARD='LVTTL')), (resource switch 1 (pins i gpio_0:2) (attrs IOSTANDARD='LVTTL')), (resource switch 2 (pins i gpio_0:3) (attrs IOSTANDARD='LVTTL')), (resource switch 3 (pins i gpio_0:4) (attrs IOSTANDARD='LVTTL')), (resource switch 4 (pins i gpio_0:5) (attrs IOSTANDARD='LVTTL')), (resource switch 5 (pins i gpio_0:6) (attrs IOSTANDARD='LVTTL')), (resource switch 6 (pins i gpio_0:7) (attrs IOSTANDARD='LVTTL')), (resource switch 7 (pins i gpio_0:8) (attrs IOSTANDARD='LVTTL')), (resource display_7seg 0 (subsignal a (pins-n o gpio_0:13)) (subsignal b (pins-n o gpio_0:14)) (subsignal c (pins-n o gpio_0:15)) (subsignal d (pins-n o gpio_0:16)) (subsignal e (pins-n o gpio_0:17)) (subsignal f (pins-n o gpio_0:18)) (subsignal g (pins-n o gpio_0:19)) (subsignal dp (pins-n o gpio_0:20)) (attrs IOSTANDARD='LVTTL')), (resource display_7seg_ctrl 0 (subsignal en (pins o gpio_0:9 gpio_0:10 gpio_0:11 gpio_0:12)) (attrs IOSTANDARD='LVTTL')), (resource audio 0 (subsignal l (pins o gpio_0:30)) (subsignal r (pins o gpio_0:29)) (attrs IOSTANDARD='LVTTL'))]

toolchain_program(products: BuildProducts, name: str) → None: Extract bitstream for fragment name from products and download it to a target.

class torii_boards.xilinx.microzed_z010.MicroZedZ010Platform(*, toolchain: Literal['Vivado', 'ISE', 'Symbiflow'] | None = None)

device = 'xc7z010'

package = 'clg400'

speed = '1'

pretty_name = 'MicroZed Z010'

description = 'Avnet MicroZed Z010 Xilinx Zynq-7010 Development Board'

resources = []

connectors = [(connector JX1 0 1=>F9 2=>J6 3=>F6 4=>G6 8=>R11 9=>R19 10=>T19 11=>T11 12=>T12 13=>T10 14=>U12 17=>U13 18=>V12 19=>V13 20=>W13 23=>T14 24=>P14 25=>T15 26=>R14 29=>Y16 30=>Y17 31=>W14 32=>Y14 35=>T16 36=>V15 37=>U17 38=>W15 41=>U14 42=>U18 43=>U15 44=>U19 47=>N18 48=>N20 49=>P19 50=>P20 53=>T20 54=>V20 55=>U20 56=>W20 61=>Y18 62=>V16 63=>Y19 64=>W16 67=>R16 68=>T17 69=>R17 70=>R18 73=>V17 74=>W18 75=>V18 76=>W19 81=>N17 82=>P15 83=>P18 84=>P16 97=>K9 98=>M9 99=>L10 100=>M10), (connector JX2 0 1=>E8 2=>E9 3=>C6 4=>D9 5=>E6 6=>B5 7=>C5 8=>C8 9=>R10 11=>C7 13=>G14 14=>J15 17=>C20 18=>B19 19=>B20 20=>A20 23=>E17 24=>D19 25=>D18 26=>D20 29=>E18 30=>F16 31=>E19 32=>F17 35=>L19 36=>M19 37=>L20 38=>M20 41=>M17 42=>K19 43=>M18 44=>J19 47=>L16 48=>K17 49=>L17 50=>K18 53=>H16 54=>J18 55=>H17 56=>H18 61=>G17 62=>F19 63=>G18 64=>F20 67=>G19 68=>J20 69=>G20 70=>H20 73=>K14 74=>H15 75=>J14 76=>G15 81=>N15 82=>L14 83=>N16 84=>L15 87=>M14 88=>K16 89=>M15 90=>J16)]

class torii_boards.xilinx.microzed_z020.MicroZedZ020Platform(*, toolchain: Literal['Vivado', 'ISE', 'Symbiflow'] | None = None)

device = 'xc7z020'

package = 'clg400'

speed = '1'

pretty_name = 'MicroZed Z020'

description = 'Avnet MicroZed Z020 Xilinx Zynq-7020 Development Board'

resources = []

connectors = [(connector JX1 0 1=>F9 2=>J6 3=>F6 4=>G6 8=>R11 9=>R19 10=>T19 11=>T11 12=>T12 13=>T10 14=>U12 17=>U13 18=>V12 19=>V13 20=>W13 23=>T14 24=>P14 25=>T15 26=>R14 29=>Y16 30=>Y17 31=>W14 32=>Y14 35=>T16 36=>V15 37=>U17 38=>W15 41=>U14 42=>U18 43=>U15 44=>U19 47=>N18 48=>N20 49=>P19 50=>P20 53=>T20 54=>V20 55=>U20 56=>W20 61=>Y18 62=>V16 63=>Y19 64=>W16 67=>R16 68=>T17 69=>R17 70=>R18 73=>V17 74=>W18 75=>V18 76=>W19 81=>N17 82=>P15 83=>P18 84=>P16 87=>U7 88=>T9 89=>V7 90=>U10 91=>V8 92=>T5 93=>W8 94=>U5 97=>K9 98=>M9 99=>L10 100=>M10), (connector JX2 0 1=>E8 2=>E9 3=>C6 4=>D9 5=>E6 6=>B5 7=>C5 8=>C8 9=>R10 11=>C7 13=>G14 14=>J15 17=>C20 18=>B19 19=>B20 20=>A20 23=>E17 24=>D19 25=>D18 26=>D20 29=>E18 30=>F16 31=>E19 32=>F17 35=>L19 36=>M19 37=>L20 38=>M20 41=>M17 42=>K19 43=>M18 44=>J19 47=>L16 48=>K17 49=>L17 50=>K18 53=>H16 54=>J18 55=>H17 56=>H18 61=>G17 62=>F19 63=>G18 64=>F20 67=>G19 68=>J20 69=>G20 70=>H20 73=>K14 74=>H15 75=>J14 76=>G15 81=>N15 82=>L14 83=>N16 84=>L15 87=>M14 88=>K16 89=>M15 90=>J16 93=>Y12 94=>V11 95=>Y13 96=>V10 97=>V6 99=>W6 100=>V5)]

class torii_boards.xilinx.nexys4ddr.Nexys4DDRPlatform(*, toolchain: Literal['Vivado', 'ISE', 'Symbiflow'] | None = None)

device = 'xc7a100t'

package = 'csg324'

speed = '1'

default_clk = 'clk100'

default_rst = 'rst'

pretty_name = 'Nexys 4 DDR'

description = 'Digilent Nexys 4 DDR Xilinx Artix7-100T Development Board'

resources = [(resource clk100 0 (pins i E3) (clock 100000000.0) (attrs IOSTANDARD='LVCMOS33')), (resource rst 0 (pins-n i C12) (attrs IOSTANDARD='LVCMOS33')), (resource switch 0 (pins i J15) (attrs IOSTANDARD='LVCMOS33')), (resource switch 1 (pins i L16) (attrs IOSTANDARD='LVCMOS33')), (resource switch 2 (pins i M13) (attrs IOSTANDARD='LVCMOS33')), (resource switch 3 (pins i R15) (attrs IOSTANDARD='LVCMOS33')), (resource switch 4 (pins i R17) (attrs IOSTANDARD='LVCMOS33')), (resource switch 5 (pins i T18) (attrs IOSTANDARD='LVCMOS33')), (resource switch 6 (pins i U18) (attrs IOSTANDARD='LVCMOS33')), (resource switch 7 (pins i R13) (attrs IOSTANDARD='LVCMOS33')), (resource switch 10 (pins i R16) (attrs IOSTANDARD='LVCMOS33')), (resource switch 11 (pins i T13) (attrs IOSTANDARD='LVCMOS33')), (resource switch 12 (pins i H6) (attrs IOSTANDARD='LVCMOS33')), (resource switch 13 (pins i U12) (attrs IOSTANDARD='LVCMOS33')), (resource switch 14 (pins i U11) (attrs IOSTANDARD='LVCMOS33')), (resource switch 15 (pins i V10) (attrs IOSTANDARD='LVCMOS33')), (resource switch 8 (pins i T8) (attrs IOSTANDARD='LVCMOS18')), (resource switch 9 (pins i U8) (attrs IOSTANDARD='LVCMOS18')), (resource led 0 (pins o H17) (attrs IOSTANDARD='LVCMOS33')), (resource led 1 (pins o K15) (attrs IOSTANDARD='LVCMOS33')), (resource led 2 (pins o J13) (attrs IOSTANDARD='LVCMOS33')), (resource led 3 (pins o N14) (attrs IOSTANDARD='LVCMOS33')), (resource led 4 (pins o R18) (attrs IOSTANDARD='LVCMOS33')), (resource led 5 (pins o V17) (attrs IOSTANDARD='LVCMOS33')), (resource led 6 (pins o U17) (attrs IOSTANDARD='LVCMOS33')), (resource led 7 (pins o U16) (attrs IOSTANDARD='LVCMOS33')), (resource led 8 (pins o V16) (attrs IOSTANDARD='LVCMOS33')), (resource led 9 (pins o T15) (attrs IOSTANDARD='LVCMOS33')), (resource led 10 (pins o U14) (attrs IOSTANDARD='LVCMOS33')), (resource led 11 (pins o T16) (attrs IOSTANDARD='LVCMOS33')), (resource led 12 (pins o V15) (attrs IOSTANDARD='LVCMOS33')), (resource led 13 (pins o V14) (attrs IOSTANDARD='LVCMOS33')), (resource led 14 (pins o V12) (attrs IOSTANDARD='LVCMOS33')), (resource led 15 (pins o V11) (attrs IOSTANDARD='LVCMOS33')), (resource rgb_led 0 (subsignal r (pins o N15)) (subsignal g (pins o M16)) (subsignal b (pins o R12)) (attrs IOSTANDARD='LVCMOS33')), (resource rgb_led 1 (subsignal r (pins o N16)) (subsignal g (pins o R11)) (subsignal b (pins o G14)) (attrs IOSTANDARD='LVCMOS33')), (resource display_7seg 0 (subsignal a (pins-n o T10)) (subsignal b (pins-n o R10)) (subsignal c (pins-n o K16)) (subsignal d (pins-n o K13)) (subsignal e (pins-n o P15)) (subsignal f (pins-n o T11)) (subsignal g (pins-n o L18)) (subsignal dp (pins-n o H15)) (attrs IOSTANDARD='LVCMOS33')), (resource display_7seg_an 0 (pins-n o J17 J18 T9 J14 P14 T14 K2 U13) (attrs IOSTANDARD='LVCMOS33')), (resource button_reset 0 (pins-n i C12) (attrs IOSTANDARD='LVCMOS33')), (resource button_center 0 (pins i N17) (attrs IOSTANDARD='LVCMOS33')), (resource button_up 0 (pins i M18) (attrs IOSTANDARD='LVCMOS33')), (resource button_left 0 (pins i P17) (attrs IOSTANDARD='LVCMOS33')), (resource button_right 0 (pins i M17) (attrs IOSTANDARD='LVCMOS33')), (resource button_down 0 (pins i P18) (attrs IOSTANDARD='LVCMOS33')), (resource vga 0 (subsignal r (pins o A3 B4 C5 A4)) (subsignal g (pins o C6 A5 B6 A6)) (subsignal b (pins o B7 C7 D7 D8)) (subsignal hs (pins o B11)) (subsignal vs (pins o B12)) (attrs IOSTANDARD='LVCMOS33')), (resource sd_card_1bit 0 (subsignal cd (pins i A1)) (subsignal clk (pins o B1)) (subsignal cmd (pins o C1)) (subsignal dat (pins io C2)) (subsignal ecd (pins i D2)) (attrs IOSTANDARD='LVCMOS33')), (resource sd_card_4bit 0 (subsignal cd (pins i A1)) (subsignal clk (pins o B1)) (subsignal cmd (pins o C1)) (subsignal dat (pins io C2 E1 F1 D2)) (attrs IOSTANDARD='LVCMOS33')), (resource sd_card_spi 0 (subsignal cd (pins i A1)) (subsignal cs (pins-n io D2)) (subsignal clk (pins o B1)) (subsignal copi (pins o C1)) (subsignal cipo (pins i C2)) (attrs IOSTANDARD='LVCMOS33')), (resource sd_card_reset 0 (pins o E2) (attrs IOSTANDARD='LVCMOS33')), (resource accelerometer 0 (subsignal cs (pins-n o D15)) (subsignal clk (pins o F15)) (subsignal copi (pins o F14)) (subsignal cipo (pins i E15)) (subsignal int (pins i B13 C16) (attrs IOSTANDARD='LVCMOS33' PULLUP='TRUE')) (attrs IOSTANDARD='LVCMOS33')), (resource temp_sensor 0 (subsignal scl (pins o C14)) (subsignal sda (pins io C15)) (subsignal int (pins i D13) (attrs PULLUP='TRUE')) (subsignal ct (pins i B14) (attrs PULLUP='TRUE')) (attrs IOSTANDARD='LVCMOS33')), (resource microphone 0 (subsignal clk (pins o J5)) (subsignal data (pins i H5)) (subsignal lr_sel (pins o F5)) (attrs IOSTANDARD='LVCMOS33')), (resource audio 0 (subsignal pwm (pins o A11)) (subsignal sd (pins-n o D12)) (attrs IOSTANDARD='LVCMOS33')), (resource uart 0 (subsignal rx (pins i C4)) (subsignal tx (pins o D4)) (subsignal rts (pins i E5)) (subsignal cts (pins o D3)) (attrs IOSTANDARD='LVCMOS33')), (resource ps2 0 (subsignal clk (pins i F4)) (subsignal dat (pins io B2)) (attrs IOSTANDARD='LVCMOS33' PULLUP='TRUE')), (resource eth 0 (subsignal mdio (pins io A9)) (subsignal mdc (pins o C9)) (subsignal reset (pins o B3)) (subsignal rxd (pins io C11 D10)) (subsignal rxerr (pins io C10)) (subsignal txd (pins o A10 A8)) (subsignal txen (pins o B9)) (subsignal crs_dv (pins io D9)) (subsignal int (pins-n io B8)) (subsignal clk (pins o D5) (clock 50000000.0)) (attrs IOSTANDARD='LVCMOS33')), (resource spi_flash_1x 0 (subsignal cs (pins-n o L13)) (subsignal clk (pins o E9)) (subsignal copi (pins o K17)) (subsignal cipo (pins i K18)) (subsignal wp (pins-n o L14)) (subsignal hold (pins-n o M14)) (attrs IOSTANDARD='LVCMOS33')), (resource spi_flash_2x 0 (subsignal cs (pins-n o L13)) (subsignal clk (pins o E9)) (subsignal dq (pins io K17 K18)) (attrs IOSTANDARD='LVCMOS33')), (resource spi_flash_4x 0 (subsignal cs (pins-n o L13)) (subsignal clk (pins o E9)) (subsignal dq (pins io K17 K18 L14 M14)) (attrs IOSTANDARD='LVCMOS33')), (resource ddr2 0 (subsignal a (pins o M4 P4 M6 T1 L3 P5 M2 N1 L4 N5 R2 K5 N6 K3)) (subsignal dq (pins io R7 V6 R8 U7 V7 R6 U6 R5 T5 U3 V5 U4 V4 T4 V1 T3) (attrs IN_TERM='UNTUNED_SPLIT_50')) (subsignal ba (pins o P2 P3 R1)) (subsignal clk (diffpairs o (p L6) (n L5)) (attrs IOSTANDARD='DIFF_SSTL18_I')) (subsignal clk_en (pins o M1)) (subsignal cs (pins-n o K6)) (subsignal we (pins-n o N2)) (subsignal ras (pins-n o N4)) (subsignal cas (pins-n o L1)) (subsignal dqs (diffpairs o (p U9 U2) (n V9 V2)) (attrs IOSTANDARD='DIFF_SSTL18_I')) (subsignal dm (pins o T6 U1)) (subsignal odt (pins o R5)) (attrs IOSTANDARD='SSTL18_I' SLEW='FAST'))]

connectors = [(connector pmod 0 1=>C17 2=>D18 3=>E18 4=>G17 7=>D17 8=>E17 9=>F18 10=>G18), (connector pmod 1 1=>D14 2=>F16 3=>G16 4=>H14 7=>E16 8=>F13 9=>G13 10=>H16), (connector pmod 2 1=>K1 2=>F6 3=>J2 4=>G6 7=>E7 8=>J3 9=>J4 10=>E6), (connector pmod 3 1=>H4 2=>H1 3=>G1 4=>G3 7=>H2 8=>G4 9=>G2 10=>F3)]

toolchain_prepare(fragment: Fragment, name: str, **kwargs) → BuildPlan: Convert the fragment and constraints recorded in this Platform into a BuildPlan.

toolchain_program(products: BuildProducts, name: str) → None: Extract bitstream for fragment name from products and download it to a target.

class torii_boards.xilinx.numato_mimas.NumatoMimasPlatform(*, toolchain: Literal['Vivado', 'ISE', 'Symbiflow'] | None = None)

device = 'xc6slx9'

package = 'tqg144'

speed = '2'

default_clk = 'clk100'

pretty_name = 'Mimas S6'

description = 'Numato Mimas S6 Xilinx Spartan6 Development Board'

resources = [(resource clk100 0 (pins i P126) (clock 100000000.0) (attrs IOSTANDARD='LVCMOS33')), (resource led 0 (pins o P119) (attrs IOSTANDARD='LVCMOS33')), (resource led 1 (pins o P118) (attrs IOSTANDARD='LVCMOS33')), (resource led 2 (pins o P117) (attrs IOSTANDARD='LVCMOS33')), (resource led 3 (pins o P116) (attrs IOSTANDARD='LVCMOS33')), (resource led 4 (pins o P115) (attrs IOSTANDARD='LVCMOS33')), (resource led 5 (pins o P114) (attrs IOSTANDARD='LVCMOS33')), (resource led 6 (pins o P112) (attrs IOSTANDARD='LVCMOS33')), (resource led 7 (pins o P111) (attrs IOSTANDARD='LVCMOS33')), (resource button 0 (pins i P124) (attrs IOSTANDARD='LVCMOS33' PULLUP='TRUE')), (resource button 1 (pins i P123) (attrs IOSTANDARD='LVCMOS33' PULLUP='TRUE')), (resource button 2 (pins i P121) (attrs IOSTANDARD='LVCMOS33' PULLUP='TRUE')), (resource button 3 (pins i P120) (attrs IOSTANDARD='LVCMOS33' PULLUP='TRUE')), (resource spi_flash_1x 0 (subsignal cs (pins-n o P38)) (subsignal clk (pins o P70)) (subsignal copi (pins o P64)) (subsignal cipo (pins i 65)) (attrs IOSTANDARD='LVCMOS33')), (resource spi_flash_2x 0 (subsignal cs (pins-n o P38)) (subsignal clk (pins o P70)) (subsignal dq (pins io P64 65)) (attrs IOSTANDARD='LVCMOS33'))]

connectors = [(connector p 1 3=>P35 4=>P34 5=>P33 6=>P32 7=>P30 8=>P29 9=>P27 10=>P26 11=>P24 12=>P23 13=>P22 14=>P21 15=>P17 16=>P16 17=>P15 18=>P14 19=>P12 20=>P11 21=>P10 22=>P9 23=>P8 24=>P7 25=>P6 26=>P5 27=>P2 28=>P1 29=>P142 30=>P141 31=>P140 32=>P139 33=>P138 34=>P137 35=>P134 36=>P133 37=>P132 38=>P131), (connector p 2 3=>P43 4=>P44 5=>P45 6=>P46 7=>P47 8=>P48 9=>P50 10=>P51 11=>P55 12=>P56 13=>P74 14=>P75 15=>P78 16=>P79 17=>P80 18=>P81 21=>P82 22=>P83 23=>P84 24=>P85 25=>P87 26=>P88 27=>P92 28=>P93 29=>P94 30=>P95 31=>P97 32=>P98 33=>P99 34=>P100 35=>P101 36=>P102 37=>P104 38=>P105)]

class torii_boards.xilinx.sk_xc6slx9.SK_XC6SLX9Platform(*, toolchain: Literal['Vivado', 'ISE', 'Symbiflow'] | None = None)

device = 'xc6slx9'

package = 'tqg144'

speed = '2'

default_clk = 'clk50'

pretty_name = 'SK-XC6SLX9'

description = 'Starterkit.ru SK-XC6SLX9 Xilinx Spartan 6 Development Board'

resources = [(resource clk50 0 (pins i P134) (clock 50000000.0) (attrs IOSTANDARD='LVCMOS33')), (resource spi_flash_1x 0 (subsignal cs (pins-n o P38)) (subsignal clk (pins o P70)) (subsignal copi (pins o P64)) (subsignal cipo (pins i 65)) (attrs IOSTANDARD='LVCMOS33')), (resource spi_flash_2x 0 (subsignal cs (pins-n o P38)) (subsignal clk (pins o P70)) (subsignal dq (pins io P64 65)) (attrs IOSTANDARD='LVCMOS33')), (resource sram 0 (subsignal cs (pins-n o P97)) (subsignal oe (pins-n o P45)) (subsignal we (pins-n o P51)) (subsignal a (pins o P39 P40 P41 P43 P44 P55 P56 P57 P58 P59 P82 P81 P80 P79 P78 P66 P62 P61 P60)) (subsignal d (pins io P46 P47 P48 P50 P75 P74 P69 P67)) (attrs IOSTANDARD='LVCMOS33'))]

connectors = [(connector x 7 3=>P34 5=>P33 6=>P32 7=>P30 8=>P29 9=>P27 10=>P26 11=>P24 12=>P23 13=>P22 14=>P21 15=>P17 16=>P16 17=>P15 18=>P14 19=>P12 20=>P11 21=>P10 22=>P9 23=>P8 24=>P7 25=>P6 26=>P5 27=>P2 28=>P1 29=>P143 30=>P144 31=>P141 32=>P142 33=>P139 34=>P140 35=>P137 36=>P138 37=>P132 38=>P133 39=>P127 40=>P131), (connector x 9 3=>P93 5=>P92 6=>P88 7=>P87 8=>P85 9=>P84 10=>P83 11=>P74 12=>P75 13=>P78 14=>P79 15=>P81 16=>P80 17=>P69 18=>P82 19=>P66 20=>P67 21=>P61 22=>P62 23=>P59 24=>P60 25=>P58 26=>P57 27=>P55 28=>P56 29=>P50 30=>P51 31=>P47 32=>P48 33=>P44 34=>P46 35=>P45 36=>P43 37=>P40 38=>P41 39=>P35 40=>P39), (connector x 8 3=>P126 5=>P123 6=>P124 7=>P120 8=>P121 9=>P118 10=>P119 11=>P116 12=>P117 13=>P114 14=>P115 15=>P111 16=>P112 17=>P104 18=>P105 19=>P101 20=>P102 21=>P99 22=>P100 23=>P97 24=>P98 25=>P94 26=>P95)]

class torii_boards.xilinx.te0714_03_50_2I.TE0714_03_50_2IPlatform(*, toolchain: Literal['Vivado', 'ISE', 'Symbiflow'] | None = None)

device = 'xc7a50t'

package = 'csg325'

speed = '2'

default_clk = 'clk25'

pretty_name = 'TE0714-03-50'

description = 'Trenz Electronic TE0714-03-50 Xilinx Artix7-50T based FPGA Module'

resources = [(resource clk25 0 (pins i T14) (clock 25000000.0) (attrs IOSTANDARD='LVCMOS18')), (resource led 0 (pins o K18) (attrs IOSTANDARD='LVCMOS18')), (resource spi_flash_1x 0 (subsignal cs (pins-n o L15)) (subsignal clk (pins o E8)) (subsignal copi (pins o K16)) (subsignal cipo (pins i K17)) (subsignal wp (pins-n o J15)) (subsignal hold (pins-n o J16)) (attrs IOSTANDARD='LVCMOS18')), (resource spi_flash_2x 0 (subsignal cs (pins-n o L15)) (subsignal clk (pins o E8)) (subsignal dq (pins io K16 K17)) (attrs IOSTANDARD='LVCMOS18')), (resource spi_flash_4x 0 (subsignal cs (pins-n o L15)) (subsignal clk (pins o E8)) (subsignal dq (pins io K16 K17 J15 J16)) (attrs IOSTANDARD='LVCMOS18'))]

connectors = [(connector JM1 0 1=>G4 2=>D6 3=>G3 4=>D5 7=>C4 8=>B2 9=>C3 10=>B1 13=>A4 14=>D2 15=>A3 16=>D1 19=>E4 20=>F2 21=>E3 22=>F1 25=>K10 26=>H2 27=>L9 28=>H1 31=>J5 32=>L5 33=>J4 34=>M5 35=>K6 36=>M2 37=>K5 38=>M1 39=>K3 40=>K2 41=>L2 42=>K1 43=>L4 44=>N1 45=>L3 46=>P1 49=>M4 50=>M6 51=>N4 52=>N6 53=>N2 54=>R2 55=>N3 56=>R1 57=>P3 58=>R3 59=>P4 60=>T2 61=>L6 62=>U1 63=>T3 64=>U2 65=>T4 67=>R5 68=>V2 69=>T5 70=>V3 71=>P5 72=>U4 73=>P6 74=>V4 75=>T7 76=>U5 77=>R7 78=>U6 79=>V6 80=>V7 81=>U7 82=>V8 85=>V9 86=>T9 87=>U9 88=>T8 89=>V11 90=>F8 91=>U11 92=>R8 93=>V12 95=>V13 96=>F12), (connector JM2 0 1=>A12 2=>B9 3=>B12 4=>A9 5=>A13 6=>B10 7=>A14 8=>A10 9=>B14 10=>B11 11=>A15 12=>C11 13=>C14 14=>C8 15=>B15 16=>D8 18=>E11 19=>A17 20=>C9 21=>B16 22=>D9 23=>B17 24=>D11 25=>C16 26=>C12 27=>C18 28=>D13 29=>C17 30=>C13 31=>D18 32=>E13 33=>E17 34=>D14 37=>E18 38=>D15 39=>F17 40=>E15 41=>F18 42=>D16 43=>G17 44=>E16 45=>F15 46=>F14 47=>G15 48=>G14 49=>H17 50=>G16 51=>H18 52=>H16 54=>A16 55=>K17 56=>J14 57=>L18 58=>K15 59=>M17 60=>M14 61=>M16 62=>N14 63=>R18 64=>N16 65=>T18 66=>N17 67=>E8 68=>K16 69=>L15 70=>J16 71=>L17 73=>J15 74=>P16 75=>N18 76=>P15 77=>P18 78=>R17 79=>T17 80=>R16 81=>U17 82=>P14 84=>R15 85=>V17 86=>T15 87=>V16 88=>T14 89=>U16 91=>U15 92=>R13 93=>U14 94=>T13 95=>V14 96=>U12 97=>U10 98=>T12 99=>L14 100=>R12)]

class torii_boards.xilinx.zturn_lite_z007s.ZTurnLiteZ007SPlatform(*, toolchain: Literal['Vivado', 'ISE', 'Symbiflow'] | None = None)

device = 'xc7z007s'

package = 'clg400'

speed = '1'

pretty_name = 'Z-Turn Lite'

description = 'Myir Z-Turn Lite Xilinx Zynq-7007 SoC Development Board'

resources = []

connectors = [(connector expansion 0 3=>B19 4=>E17 5=>A20 6=>D18 9=>E18 10=>D19 11=>E19 12=>D20 13=>G17 14=>F16 15=>G18 16=>F17 21=>J18 22=>J20 23=>H18 24=>H20 25=>C20 26=>K17 27=>B20 28=>K18 31=>G19 32=>K19 33=>G20 34=>J19 35=>F19 36=>H15 37=>F20 38=>G15 41=>L16 42=>K14 43=>L17 44=>J14 45=>L19 46=>H16 47=>L20 48=>H17 51=>K16 52=>L14 53=>J16 54=>L15 55=>M17 56=>M14 57=>M18 58=>M15 61=>N17 62=>P15 63=>P18 64=>P16 65=>M19 66=>N15 67=>M20 68=>N16 71=>N18 73=>P19 74=>R16 75=>N20 76=>R17 77=>P20 78=>T20 80=>U20 83=>T16 84=>V20 85=>U17 86=>W20 87=>U18 88=>T17 89=>U19 90=>R18 93=>W18 94=>V17 95=>W19 96=>V18 97=>U14 98=>V16 99=>U15 100=>W16 103=>V15 104=>Y18 105=>W15 106=>Y19 107=>Y16 108=>W14 109=>Y17 110=>Y14)]

class torii_boards.xilinx.zturn_lite_z010.ZTurnLiteZ010Platform(*, toolchain: Literal['Vivado', 'ISE', 'Symbiflow'] | None = None)

device = 'xc7z010'

pretty_name = 'Z-Turn Lite'

description = 'Myir Z-Turn Lite Xilinx Zynq-7010 SoC Development Board'