Lattice Boards

The torii.platform.vendor.lattice.ecp5 module provides a base platform to support Lattice ECP5 devices with the Trellis and Diamond toolchains.

The torii.platform.vendor.lattice.ice40 module provides a base platform to support Lattice iCE40 devices with the IceStorm and iCECube2 toolchains.

The torii.platform.vendor.lattice.machxo_2_3l module provides a base platform to support Lattice MachXO2 and MachXO3L devices with the Diamond toolchain.

class torii_boards.lattice.blackice_ii.BlackIceIIPlatform(*, toolchain: Literal['IceStorm', 'LSE-iCECube2', 'Synplify-iCECube2'] = 'IceStorm')
device = 'iCE40HX4K'
package = 'TQ144'
default_clk = 'clk100'
pretty_name = 'BlackIce II'
description = 'myStorm BlackIce II Lattice iCE40-HX4k Development Board'
resources = [(resource clk100 0 (pins i 129) (clock 100000000.0) (attrs GLOBAL=True IO_STANDARD='SB_LVCMOS')), (resource led 0 (pins o 71) (attrs IO_STANDARD='SB_LVCMOS')), (resource led 1 (pins o 67) (attrs IO_STANDARD='SB_LVCMOS')), (resource led 2 (pins o 68) (attrs IO_STANDARD='SB_LVCMOS')), (resource led 3 (pins o 70) (attrs IO_STANDARD='SB_LVCMOS')), (resource led_b 0 (pins o 71) (attrs IO_STANDARD='SB_LVCMOS')), (resource led_g 0 (pins o 67) (attrs IO_STANDARD='SB_LVCMOS')), (resource led_o 0 (pins o 68) (attrs IO_STANDARD='SB_LVCMOS')), (resource led_r 0 (pins o 70) (attrs IO_STANDARD='SB_LVCMOS')), (resource button 0 (pins-n i 63) (attrs IO_STANDARD='SB_LVCMOS')), (resource button 1 (pins-n i 64) (attrs IO_STANDARD='SB_LVCMOS')), (resource switch 0 (pins-n i 37) (attrs IO_STANDARD='SB_LVCMOS')), (resource switch 1 (pins-n i 38) (attrs IO_STANDARD='SB_LVCMOS')), (resource switch 2 (pins-n i 39) (attrs IO_STANDARD='SB_LVCMOS')), (resource switch 3 (pins-n i 41) (attrs IO_STANDARD='SB_LVCMOS')), (resource uart 0 (subsignal rx (pins i 88)) (subsignal tx (pins o 85)) (subsignal rts (pins i 91)) (subsignal cts (pins o 94)) (attrs IO_STANDARD='SB_LVCMOS' PULLUP=1)), (resource sram 0 (subsignal cs (pins-n o 23)) (subsignal oe (pins-n o 29)) (subsignal we (pins-n o 120)) (subsignal a (pins o 137 138 139 141 142 42 43 44 73 74 75 76 115 116 117 118 119 78)) (subsignal d (pins io 136 135 134 130 125 124 122 121 62 61 60 56 55 48 47 45)) (subsignal dm (pins-n o 24 28)) (attrs IO_STANDARD='SB_LVCMOS'))]
connectors = [(connector pmod 0 1=>94 2=>91 3=>88 4=>85 7=>95 8=>93 9=>90 10=>87), (connector pmod 1 1=>105 2=>102 3=>99 4=>97 7=>104 8=>101 9=>98 10=>96), (connector pmod 2 1=>143 2=>114 3=>112 4=>107 7=>144 8=>113 9=>110 10=>106), (connector pmod 3 1=>10 2=>9 3=>2 4=>1 7=>8 8=>7 9=>4 10=>3), (connector pmod 4 1=>20 2=>19 3=>16 4=>15 7=>18 8=>17 9=>12 10=>11), (connector pmod 5 1=>34 2=>33 3=>22 4=>21 7=>32 8=>31 9=>26 10=>25), (connector pmod 6 1=>37 2=>38 3=>39 4=>41), (connector pmod 7 1=>71 2=>67 3=>68 4=>70)]
toolchain_program(products: BuildProducts, name: str) → None

Extract bitstream for fragment name from products and download it to a target.

class torii_boards.lattice.blackice.BlackIcePlatform(*, toolchain: Literal['IceStorm', 'LSE-iCECube2', 'Synplify-iCECube2'] = 'IceStorm')
device = 'iCE40HX4K'
package = 'TQ144'
default_clk = 'clk100'
pretty_name = 'BlackIce'
description = 'myStorm BlackIce Lattice iCE40-HX4k Development Board'
resources = [(resource clk100 0 (pins i 129) (clock 100000000.0) (attrs GLOBAL=True IO_STANDARD='SB_LVCMOS')), (resource led 0 (pins o 71) (attrs IO_STANDARD='SB_LVCMOS')), (resource led 1 (pins o 67) (attrs IO_STANDARD='SB_LVCMOS')), (resource led 2 (pins o 68) (attrs IO_STANDARD='SB_LVCMOS')), (resource led 3 (pins o 70) (attrs IO_STANDARD='SB_LVCMOS')), (resource led_b 0 (pins o 71) (attrs IO_STANDARD='SB_LVCMOS')), (resource led_g 0 (pins o 67) (attrs IO_STANDARD='SB_LVCMOS')), (resource led_o 0 (pins o 68) (attrs IO_STANDARD='SB_LVCMOS')), (resource led_r 0 (pins o 70) (attrs IO_STANDARD='SB_LVCMOS')), (resource button 0 (pins-n i 63) (attrs IO_STANDARD='SB_LVCMOS')), (resource button 1 (pins-n i 64) (attrs IO_STANDARD='SB_LVCMOS')), (resource switch 0 (pins-n i 37) (attrs IO_STANDARD='SB_LVCMOS')), (resource switch 1 (pins-n i 38) (attrs IO_STANDARD='SB_LVCMOS')), (resource switch 2 (pins-n i 39) (attrs IO_STANDARD='SB_LVCMOS')), (resource switch 3 (pins-n i 41) (attrs IO_STANDARD='SB_LVCMOS')), (resource uart 0 (subsignal rx (pins i 88)) (subsignal tx (pins o 85)) (attrs IO_STANDARD='SB_LVCMOS' PULLUP=1)), (resource sram 0 (subsignal cs (pins-n o 136)) (subsignal oe (pins-n o 45)) (subsignal we (pins-n o 120)) (subsignal a (pins o 137 138 139 141 142 42 43 44 73 74 75 76 115 116 117 118 119 78)) (subsignal d (pins io 135 134 130 128 125 124 122 121 61 60 56 55 52 49 48 47)) (attrs IO_STANDARD='SB_LVCMOS'))]
connectors = [(connector pmod 0 1=>94 2=>91 3=>88 4=>85 7=>95 8=>93 9=>90 10=>87), (connector pmod 1 1=>105 2=>102 3=>99 4=>97 7=>104 8=>101 9=>98 10=>96), (connector pmod 2 1=>143 2=>114 3=>112 4=>107 7=>144 8=>113 9=>110 10=>106), (connector pmod 3 1=>10 2=>9 3=>2 4=>1 7=>8 8=>7 9=>4 10=>3), (connector pmod 4 1=>20 2=>19 3=>16 4=>15 7=>18 8=>17 9=>12 10=>11), (connector pmod 5 1=>34 2=>33 3=>22 4=>21 7=>32 8=>31 9=>26 10=>25), (connector pmod 6 1=>29 2=>28 3=>24 4=>23), (connector pmod 7 1=>71 2=>67 3=>68 4=>70)]
toolchain_program(products: BuildProducts, name: str) → None

Extract bitstream for fragment name from products and download it to a target.

class torii_boards.lattice.colorlight_5a75b_r7_0.Colorlight_5A75B_R70Platform(*, toolchain: Literal['Trellis', 'Diamond'] = 'Trellis')
device = 'LFE5U-25F'
package = 'BG256'
speed = '6'
default_clk = 'clk25'
pretty_name = 'Colorlight 5A-75B'
description = 'Colorlight 5A-75B Lattice ECP5-25F FPGA Board'
resources = [(resource clk25 0 (pins i P6) (clock 25000000.0) (attrs IO_TYPE='LVCMOS33')), (resource led 0 (pins-n o P11) (attrs IO_TYPE='LVCMOS33' DRIVE='4')), (resource button 0 (pins-n i M13) (attrs IO_TYPE='LVCMOS33' PULLMODE='UP')), (resource uart 0 (subsignal rx (pins i M13)) (subsignal tx (pins o P11)) (attrs IO_TYPE='LVCMOS33')), (resource spi_flash 0 (subsignal cs (pins-n o N8)) (subsignal cipo (pins i T8)) (subsignal copi (pins o T7)) (attrs IO_TYPE='LVCMOS33')), (resource sdram 0 (subsignal clk (pins o C6)) (subsignal we (pins-n o C7)) (subsignal ras (pins-n o D7)) (subsignal cas (pins-n o E7)) (subsignal ba (pins o A7)) (subsignal a (pins o A9 E10 B12 D13 C12 D11 D10 E9 D9 B7 C8)) (subsignal dq (pins io B13 C11 C10 A11 C9 E8 B6 B9 A6 B5 A5 B4 B3 C3 A2 B2 E2 D3 A4 E4 D4 C4 E5 D5 E6 D6 D8 A8 B8 B10 B11 E11)) (attrs PULLMODE='NONE' DRIVE='4' SLEWRATE='FAST' IO_TYPE='LVCMOS33')), (resource eth_rgmii 0 (subsignal rst (pins-n o P5)) (subsignal mdc (pins o P3)) (subsignal mdio (pins io T2)) (subsignal tx_clk (pins o M2)) (subsignal tx_ctl (pins o M3)) (subsignal tx_data (pins o L1 L3 P2 L4)) (subsignal rx_clk (pins i M1)) (subsignal rx_ctl (pins i N6)) (subsignal rx_data (pins i N1 M5 N5 M6)) (attrs IO_TYPE='LVCMOS33')), (resource eth_rgmii 1 (subsignal rst (pins-n o P5)) (subsignal mdc (pins o P3)) (subsignal mdio (pins io T2)) (subsignal tx_clk (pins o M12)) (subsignal tx_ctl (pins o R15)) (subsignal tx_data (pins o T14 R12 R13 R14)) (subsignal rx_clk (pins i M16)) (subsignal rx_ctl (pins i L15)) (subsignal rx_data (pins i P13 N13 P14 M15)) (attrs IO_TYPE='LVCMOS33'))]
connectors = [(connector j 1 1=>F3 2=>F1 3=>G3 5=>G2 6=>H3 7=>H5 8=>F15 9=>L2 10=>K1 11=>J5 12=>K2 13=>B16 14=>J14 15=>F12), (connector j 2 1=>J4 2=>K3 3=>G1 5=>K4 6=>C2 7=>E3 8=>F15 9=>L2 10=>K1 11=>J5 12=>K2 13=>B16 14=>J14 15=>F12), (connector j 3 1=>H4 2=>K5 3=>P1 5=>R1 6=>L5 7=>F2 8=>F15 9=>L2 10=>K1 11=>J5 12=>K2 13=>B16 14=>J14 15=>F12), (connector j 4 1=>P4 2=>R2 3=>M8 5=>M9 6=>T6 7=>R6 8=>F15 9=>L2 10=>K1 11=>J5 12=>K2 13=>B16 14=>J14 15=>F12), (connector j 5 1=>M11 2=>N11 3=>P12 5=>K15 6=>N12 7=>L16 8=>F15 9=>L2 10=>K1 11=>J5 12=>K2 13=>B16 14=>J14 15=>F12), (connector j 6 1=>K16 2=>J15 3=>J16 5=>J12 6=>H15 7=>G16 8=>F15 9=>L2 10=>K1 11=>J5 12=>K2 13=>B16 14=>J14 15=>F12), (connector j 7 1=>H13 2=>J13 3=>H12 5=>G14 6=>H14 7=>G15 8=>F15 9=>L2 10=>K1 11=>J5 12=>K2 13=>B16 14=>J14 15=>F12), (connector j 8 1=>A15 2=>F16 3=>A14 5=>E13 6=>B14 7=>A13 8=>F15 9=>L2 10=>K1 11=>J5 12=>K2 13=>B16 14=>J14 15=>F12), (connector j 19 2=>M13 5=>P11)]
property required_tools: List[str]
toolchain_prepare(fragment: Fragment, name: str, **kwargs) → BuildPlan

Convert the fragment and constraints recorded in this Platform into a BuildPlan.

toolchain_program(products: BuildProducts, name: str) → None

Extract bitstream for fragment name from products and download it to a target.

class torii_boards.lattice.ecp5_5g_evn.ECP55GEVNPlatform(*, VCCIO1: Literal['3V3', '2V5'] = '2V5', VCCIO6: Literal['3V3', '2V5'] = '3V3', **kwargs)
device = 'LFE5UM5G-85F'
package = 'BG381'
speed = '8'
default_clk = 'clk12'
default_rst = 'rst'
pretty_name = 'ECP55GEVN'
description = 'ECP55GEVN Lattice ECP5-5G-85F Evaluation Board'
bank1_iostandard() → str
bank6_iostandard() → str
resources = [(resource rst 0 (pins-n i G2) (attrs IO_TYPE='LVCMOS33')), (resource clk12 0 (pins i A10) (clock 12000000.0) (attrs IO_TYPE='LVCMOS33')), (resource extclk 0 (pins i B11) (attrs IO_TYPE='LVCMOS33')), (resource led 0 (pins-n o A13) (attrs IO_TYPE=<function ECP55GEVNPlatform.bank1_iostandard>)), (resource led 1 (pins-n o A12) (attrs IO_TYPE=<function ECP55GEVNPlatform.bank1_iostandard>)), (resource led 2 (pins-n o B19) (attrs IO_TYPE=<function ECP55GEVNPlatform.bank1_iostandard>)), (resource led 3 (pins-n o A18) (attrs IO_TYPE=<function ECP55GEVNPlatform.bank1_iostandard>)), (resource led 4 (pins-n o B18) (attrs IO_TYPE=<function ECP55GEVNPlatform.bank1_iostandard>)), (resource led 5 (pins-n o C17) (attrs IO_TYPE=<function ECP55GEVNPlatform.bank1_iostandard>)), (resource led 6 (pins-n o A17) (attrs IO_TYPE=<function ECP55GEVNPlatform.bank1_iostandard>)), (resource led 7 (pins-n o B17) (attrs IO_TYPE=<function ECP55GEVNPlatform.bank1_iostandard>)), (resource button 0 (pins-n i P4) (attrs IO_TYPE=<function ECP55GEVNPlatform.bank6_iostandard>)), (resource switch 1 (pins-n i J1) (attrs IO_TYPE=<function ECP55GEVNPlatform.bank6_iostandard>)), (resource switch 2 (pins-n i H1) (attrs IO_TYPE=<function ECP55GEVNPlatform.bank6_iostandard>)), (resource switch 3 (pins-n i K1) (attrs IO_TYPE=<function ECP55GEVNPlatform.bank6_iostandard>)), (resource switch 4 (pins-n i E15) (attrs IO_TYPE=<function ECP55GEVNPlatform.bank1_iostandard>)), (resource switch 5 (pins-n i D16) (attrs IO_TYPE=<function ECP55GEVNPlatform.bank1_iostandard>)), (resource switch 6 (pins-n i B16) (attrs IO_TYPE=<function ECP55GEVNPlatform.bank1_iostandard>)), (resource switch 7 (pins-n i C16) (attrs IO_TYPE=<function ECP55GEVNPlatform.bank1_iostandard>)), (resource switch 8 (pins-n i A16) (attrs IO_TYPE=<function ECP55GEVNPlatform.bank1_iostandard>)), (resource uart 0 (subsignal rx (pins i P2)) (subsignal tx (pins o P3)) (attrs IO_TYPE=<function ECP55GEVNPlatform.bank6_iostandard> PULLMODE='UP')), (resource spi_flash_1x 0 (subsignal cs (pins-n o R2)) (subsignal clk (pins o U3)) (subsignal copi (pins o W2)) (subsignal cipo (pins i V2)) (subsignal wp (pins-n o Y2)) (subsignal hold (pins-n o W1)) (attrs IO_TYPE='LVCMOS33')), (resource spi_flash_2x 0 (subsignal cs (pins-n o R2)) (subsignal clk (pins o U3)) (subsignal dq (pins io W2 V2)) (attrs IO_TYPE='LVCMOS33')), (resource spi_flash_4x 0 (subsignal cs (pins-n o R2)) (subsignal clk (pins o U3)) (subsignal dq (pins io W2 V2 Y2 W1)) (attrs IO_TYPE='LVCMOS33')), (resource serdes 0 (subsignal tx (diffpairs o (p W4) (n W5))) (subsignal rx (diffpairs i (p Y5) (n Y6)))), (resource serdes 1 (subsignal tx (diffpairs o (p W8) (n W9))) (subsignal rx (diffpairs i (p Y7) (n Y8)))), (resource serdes 2 (subsignal tx (diffpairs o (p W13) (n W14))) (subsignal rx (diffpairs i (p Y14) (n Y15)))), (resource serdes 3 (subsignal tx (diffpairs o (p W17) (n W18))) (subsignal rx (diffpairs i (p Y16) (n Y17)))), (resource serdes_clk 0 (diffpairs i (p Y11) (n Y12))), (resource serdes_clk 1 (diffpairs i (p Y19) (n W20)))]
connectors = [(connector J 39 4=>D15 5=>B15 6=>C15 7=>B13 8=>B20 9=>D11 10=>E11 11=>B12 12=>C12 13=>D12 14=>E12 15=>C13 16=>D13 17=>E13 18=>A14 19=>A9 20=>B10 29=>E7 31=>A11 33=>A19), (connector J 40 1=>K2 3=>A15 4=>F1 5=>H2 6=>G1 7=>J4 8=>J5 9=>J3 10=>K3 11=>L4 12=>L5 13=>M4 14=>N5 15=>N4 16=>P5 17=>N3 18=>M3 21=>K5- 22=>M5 24=>L3 26=>N2 27=>M1 28=>L2 30=>L1 31=>N1 32=>C14 34=>P1 35=>E14 36=>D14 38=>K4), (connector J 6 1=>K16 2=>J16 3=>H17 4=>J17 5=>H18 6=>H16 8=>G18 9=>G16 10=>F17), (connector J 3 1=>F19 2=>F20 3=>E20 4=>E19 5=>D19 6=>D20 7=>C20 8=>K17), (connector J 7 1=>C18 3=>D17), (connector J 4 1=>F18 2=>E17 3=>E18 4=>D18 5=>F16 6=>E16), (connector JP 8 3=>T17 5=>U16 7=>U17 8=>P18 10=>N20 11=>N19 12=>T16 13=>M18 15=>N17 16=>P17 18=>M17 19=>U20 21=>T19 22=>N18 23=>R20 24=>U19 26=>R18 27=>L18 28=>L17 29=>U18 31=>T18 32=>T20 33=>P20 35=>R17 36=>P19 37=>N16 38=>P16 40=>R16), (connector J 5 3=>H20 4=>G19 7=>K18 8=>J18 11=>K19 12=>J19 15=>K20 16=>J20 19=>G20), (connector J 8 3=>L19 4=>M19 5=>L20 6=>M20 7=>L16), (connector J 32 5=>A5 6=>A4 9=>C5 10=>B5 13=>B4 14=>C4 17=>B3 18=>A3 21=>D5 22=>E4 25=>D3 26=>C3 29=>E3F4 32=>F5 33=>E5 36=>B1 37=>A2), (connector J 33 5=>C2 6=>B2 9=>D1 10=>C1 13=>E1 14=>D2 17=>G5 18=>H4 21=>H3 22=>H5 25=>F3 26=>G3 29=>E2 30=>F2), (connector J 30 2=>B6 3=>D9 4=>C9 5=>E9 6=>D10 7=>A6 8=>E10), (connector J 31 1=>C6 2=>C7 3=>E8 4=>D8 7=>C8 8=>B8 9=>A7 10=>A8), (connector J 1 2=>V4 3=>R5 6=>U5 8=>T5), (connector J 38 1=>W3 2=>R2 3=>T3 4=>Y3 5=>R1 6=>V3 7=>T1 8=>V2 9=>U1 10=>W2 11=>V1 12=>T2 13=>W1 14=>U2 15=>Y2 16=>R2 17=>U3 18=>R3)]
property file_templates: Dict[str, str]
toolchain_program(products: BuildProducts, name: str) → None

Extract bitstream for fragment name from products and download it to a target.

class torii_boards.lattice.ecpix5.ECPIX585Platform(*, toolchain: Literal['Trellis', 'Diamond'] = 'Trellis')
device = 'LFE5UM5G-85F'
pretty_name = 'ECPIX5 85F'
description = 'Lambda Concept ECPIX5 85F Lattice ECP5-5G-85F Development Board'
resources = [(resource rst 0 (pins-n i AB1) (attrs IO_TYPE='LVCMOS33')), (resource clk100 0 (pins i K23) (clock 100000000.0) (attrs IO_TYPE='LVCMOS33')), (resource rgb_led 0 (subsignal r (pins-n o T23)) (subsignal g (pins-n o R21)) (subsignal b (pins-n o T22)) (attrs IO_TYPE='LVCMOS33' PULLMODE='UP')), (resource rgb_led 1 (subsignal r (pins-n o U21)) (subsignal g (pins-n o W21)) (subsignal b (pins-n o T24)) (attrs IO_TYPE='LVCMOS33' PULLMODE='UP')), (resource rgb_led 2 (subsignal r (pins-n o K21)) (subsignal g (pins-n o K24)) (subsignal b (pins-n o M21)) (attrs IO_TYPE='LVCMOS33' PULLMODE='UP')), (resource rgb_led 3 (subsignal r (pins-n o P21)) (subsignal g (pins-n o R23)) (subsignal b (pins-n o P22)) (attrs IO_TYPE='LVCMOS33' PULLMODE='UP')), (resource uart 0 (subsignal rx (pins i R26)) (subsignal tx (pins o R24)) (attrs IO_TYPE='LVCMOS33' PULLMODE='UP')), (resource spi_flash_1x 0 (subsignal cs (pins-n o AA2)) (subsignal clk (pins o AE3)) (subsignal copi (pins o AD2)) (subsignal cipo (pins i AE2)) (subsignal wp (pins-n o AF2)) (subsignal hold (pins-n o AE1)) (attrs IO_TYPE='LVCMOS33')), (resource spi_flash_2x 0 (subsignal cs (pins-n o AA2)) (subsignal clk (pins o AE3)) (subsignal dq (pins io AD2 AE2)) (attrs IO_TYPE='LVCMOS33')), (resource spi_flash_4x 0 (subsignal cs (pins-n o AA2)) (subsignal clk (pins o AE3)) (subsignal dq (pins io AD2 AE2 AF2 AE1)) (attrs IO_TYPE='LVCMOS33')), (resource eth_rgmii 0 (subsignal rst (pins-n o C13)) (subsignal mdio (pins io A13)) (subsignal mdc (pins o C11)) (subsignal tx_clk (pins o A12)) (subsignal tx_ctrl (pins o C9)) (subsignal tx_data (pins o D8 C8 B8 A8)) (subsignal rx_clk (pins i E11)) (subsignal rx_ctrl (pins i A11)) (subsignal rx_data (pins i B11 A10 B10 A9)) (attrs IO_TYPE='LVCMOS33')), (resource eth_int 0 (pins-n i B13) (attrs IO_TYPE='LVCMOS33')), (resource ddr3 0 (subsignal clk (diffpairs o (p H3) (n J3)) (attrs IO_TYPE='SSTL15D_I')) (subsignal clk_en (pins o P1)) (subsignal we (pins-n o R3)) (subsignal ras (pins-n o T3)) (subsignal cas (pins-n o P2)) (subsignal a (pins o T5 M3 L3 V6 K2 W6 K3 L1 H2 L2 N1 J1 M1 K1 H1)) (subsignal ba (pins o U6 N3 N4)) (subsignal dqs (diffpairs io (p V4 V1) (n U5 U2)) (attrs IO_TYPE='SSTL15D_I' TERMINATION='OFF' DIFFRESISTOR='100')) (subsignal dq (pins io T4 W4 R4 W5 R6 P6 P5 P4 R1 W3 T2 V3 U3 W1 T1 W2) (attrs TERMINATION='75')) (subsignal dm (pins o U4 U1)) (subsignal odt (pins o P3)) (attrs IO_TYPE='SSTL15_I' SLEWRATE='FAST')), (resource sata 0 (subsignal tx (diffpairs o (p AD16) (n AD17))) (subsignal rx (diffpairs i (p AF15) (n AF16))) (attrs IO_TYPE='LVDS')), (resource ulpi 0 (subsignal data (pins io M26 L25 L26 K25 K26 J23 P25 H25)) (subsignal clk (pins i H24) (clock 60000000.0)) (subsignal dir (pins i F22)) (subsignal nxt (pins i F23)) (subsignal stp (pins o H23)) (subsignal rst (pins o E23)) (attrs IO_TYPE='LVCMOS33' SLEWRATE='SLOW')), (resource usbc_cfg 0 (subsignal scl (pins io D24)) (subsignal sda (pins io C24)) (subsignal dir (pins i B23)) (subsignal id (pins i D23)) (subsignal int (pins-n i B24)) (attrs IO_TYPE='LVCMOS33')), (resource usbc_mux 0 (subsignal en (pins oe C23)) (subsignal amsel (pins oe B26)) (subsignal pol (pins o D26)) (subsignal lna (diffpairs i (p AF9) (n AF10)) (attrs IO_TYPE='LVCMOS18D')) (subsignal lnb (diffpairs o (p AD10) (n AD11)) (attrs IO_TYPE='LVCMOS18D')) (subsignal lnc (diffpairs o (p AD7) (n AD8)) (attrs IO_TYPE='LVCMOS18D')) (subsignal lnd (diffpairs i (p AF6) (n AF7)) (attrs IO_TYPE='LVCMOS18D')) (attrs IO_TYPE='LVCMOS33')), (resource it6613e 0 (subsignal rst (pins-n o N6)) (subsignal scl (pins io C17)) (subsignal sda (pins io E17)) (subsignal pclk (pins o C1)) (subsignal vsync (pins o A4)) (subsignal hsync (pins o B4)) (subsignal de (pins o A3)) (subsignal d (subsignal b (pins o AD25 AC26 AB24 AB25 B3 C3 D3 B1 C2 D2 D1 E3)) (subsignal g (pins o AA23 AA22 AA24 AA25 E1 F2 F1 D17 D16 E16 J6 H6)) (subsignal r (pins o AD26 AE25 AF25 AE26 E10 D11 D10 C10 D9 E8 H5 J4))) (subsignal mclk (pins o E19)) (subsignal sck (pins o D6)) (subsignal ws (pins o C6)) (subsignal i2s (pins o A6 B6 A5 C5)) (subsignal int (pins-n i C4)) (attrs IO_TYPE='LVTTL33'))]
class torii_boards.lattice.ecpix5.ECPIX545Platform(*, toolchain: Literal['Trellis', 'Diamond'] = 'Trellis')
device = 'LFE5UM5G-45F'
pretty_name = 'ECPIX5 45F'
description = 'Lambda Concept ECPIX5 45F Lattice ECP5-5G-45F Development Board'
resources = [(resource rst 0 (pins-n i AB1) (attrs IO_TYPE='LVCMOS33')), (resource clk100 0 (pins i K23) (clock 100000000.0) (attrs IO_TYPE='LVCMOS33')), (resource rgb_led 0 (subsignal r (pins-n o T23)) (subsignal g (pins-n o R21)) (subsignal b (pins-n o T22)) (attrs IO_TYPE='LVCMOS33' PULLMODE='UP')), (resource rgb_led 1 (subsignal r (pins-n o U21)) (subsignal g (pins-n o W21)) (subsignal b (pins-n o T24)) (attrs IO_TYPE='LVCMOS33' PULLMODE='UP')), (resource rgb_led 2 (subsignal r (pins-n o K21)) (subsignal g (pins-n o K24)) (subsignal b (pins-n o M21)) (attrs IO_TYPE='LVCMOS33' PULLMODE='UP')), (resource rgb_led 3 (subsignal r (pins-n o P21)) (subsignal g (pins-n o R23)) (subsignal b (pins-n o P22)) (attrs IO_TYPE='LVCMOS33' PULLMODE='UP')), (resource uart 0 (subsignal rx (pins i R26)) (subsignal tx (pins o R24)) (attrs IO_TYPE='LVCMOS33' PULLMODE='UP')), (resource spi_flash_1x 0 (subsignal cs (pins-n o AA2)) (subsignal clk (pins o AE3)) (subsignal copi (pins o AD2)) (subsignal cipo (pins i AE2)) (subsignal wp (pins-n o AF2)) (subsignal hold (pins-n o AE1)) (attrs IO_TYPE='LVCMOS33')), (resource spi_flash_2x 0 (subsignal cs (pins-n o AA2)) (subsignal clk (pins o AE3)) (subsignal dq (pins io AD2 AE2)) (attrs IO_TYPE='LVCMOS33')), (resource spi_flash_4x 0 (subsignal cs (pins-n o AA2)) (subsignal clk (pins o AE3)) (subsignal dq (pins io AD2 AE2 AF2 AE1)) (attrs IO_TYPE='LVCMOS33')), (resource eth_rgmii 0 (subsignal rst (pins-n o C13)) (subsignal mdio (pins io A13)) (subsignal mdc (pins o C11)) (subsignal tx_clk (pins o A12)) (subsignal tx_ctrl (pins o C9)) (subsignal tx_data (pins o D8 C8 B8 A8)) (subsignal rx_clk (pins i E11)) (subsignal rx_ctrl (pins i A11)) (subsignal rx_data (pins i B11 A10 B10 A9)) (attrs IO_TYPE='LVCMOS33')), (resource eth_int 0 (pins-n i B13) (attrs IO_TYPE='LVCMOS33')), (resource ddr3 0 (subsignal clk (diffpairs o (p H3) (n J3)) (attrs IO_TYPE='SSTL15D_I')) (subsignal clk_en (pins o P1)) (subsignal we (pins-n o R3)) (subsignal ras (pins-n o T3)) (subsignal cas (pins-n o P2)) (subsignal a (pins o T5 M3 L3 V6 K2 W6 K3 L1 H2 L2 N1 J1 M1 K1 H1)) (subsignal ba (pins o U6 N3 N4)) (subsignal dqs (diffpairs io (p V4 V1) (n U5 U2)) (attrs IO_TYPE='SSTL15D_I' TERMINATION='OFF' DIFFRESISTOR='100')) (subsignal dq (pins io T4 W4 R4 W5 R6 P6 P5 P4 R1 W3 T2 V3 U3 W1 T1 W2) (attrs TERMINATION='75')) (subsignal dm (pins o U4 U1)) (subsignal odt (pins o P3)) (attrs IO_TYPE='SSTL15_I' SLEWRATE='FAST')), (resource sata 0 (subsignal tx (diffpairs o (p AD16) (n AD17))) (subsignal rx (diffpairs i (p AF15) (n AF16))) (attrs IO_TYPE='LVDS')), (resource ulpi 0 (subsignal data (pins io M26 L25 L26 K25 K26 J23 P25 H25)) (subsignal clk (pins i H24) (clock 60000000.0)) (subsignal dir (pins i F22)) (subsignal nxt (pins i F23)) (subsignal stp (pins o H23)) (subsignal rst (pins o E23)) (attrs IO_TYPE='LVCMOS33' SLEWRATE='SLOW')), (resource usbc_cfg 0 (subsignal scl (pins io D24)) (subsignal sda (pins io C24)) (subsignal dir (pins i B23)) (subsignal id (pins i D23)) (subsignal int (pins-n i B24)) (attrs IO_TYPE='LVCMOS33')), (resource usbc_mux 0 (subsignal en (pins oe C23)) (subsignal amsel (pins oe B26)) (subsignal pol (pins o D26)) (subsignal lna (diffpairs i (p AF9) (n AF10)) (attrs IO_TYPE='LVCMOS18D')) (subsignal lnb (diffpairs o (p AD10) (n AD11)) (attrs IO_TYPE='LVCMOS18D')) (subsignal lnc (diffpairs o (p AD7) (n AD8)) (attrs IO_TYPE='LVCMOS18D')) (subsignal lnd (diffpairs i (p AF6) (n AF7)) (attrs IO_TYPE='LVCMOS18D')) (attrs IO_TYPE='LVCMOS33')), (resource it6613e 0 (subsignal rst (pins-n o N6)) (subsignal scl (pins io C17)) (subsignal sda (pins io E17)) (subsignal pclk (pins o C1)) (subsignal vsync (pins o A4)) (subsignal hsync (pins o B4)) (subsignal de (pins o A3)) (subsignal d (subsignal b (pins o B3 C3 D3 B1 C2 D2 D1 E3)) (subsignal g (pins o E1 F2 F1 D17 D16 E16 J6 H6)) (subsignal r (pins o E10 D11 D10 C10 D9 E8 H5 J4))) (subsignal mclk (pins o E19)) (subsignal sck (pins o D6)) (subsignal ws (pins o C6)) (subsignal i2s (pins o A6 B6 A5 C5)) (subsignal int (pins-n i C4)) (attrs IO_TYPE='LVTTL33'))]
class torii_boards.lattice.fomu_hacker.FomuHackerPlatform(*, toolchain: Literal['IceStorm', 'LSE-iCECube2', 'Synplify-iCECube2'] = 'IceStorm')
device = 'iCE40UP5K'
package = 'UWG30'
default_clk = 'clk48'
pretty_name = 'FOMU Hacker'
description = 'Im Tomu FPGA Hacker Edition Lattice iCE40 UP5K FPGA Board'
resources = [(resource clk48 0 (pins i F5) (clock 48000000.0) (attrs GLOBAL=True IO_STANDARD='SB_LVCMOS')), (resource led 0 (pins-n o A5) (attrs IO_STANDARD='SB_LVCMOS')), (resource rgb_led 0 (subsignal r (pins-n o C5)) (subsignal g (pins-n o B5)) (subsignal b (pins-n o A5)) (attrs IO_STANDARD='SB_LVCMOS')), (resource usb 0 (subsignal d_p (pins io A4)) (subsignal d_n (pins io A2)) (subsignal pullup (pins o D5)) (attrs IO_STANDARD='SB_LVCMOS')), (resource spi_flash_1x 0 (subsignal cs (pins-n o C1)) (subsignal clk (pins o D1)) (subsignal copi (pins o F1)) (subsignal cipo (pins i E1)) (attrs IO_STANDARD='SB_LVCMOS')), (resource spi_flash_2x 0 (subsignal cs (pins-n o C1)) (subsignal clk (pins o D1)) (subsignal dq (pins io F1 E1)) (attrs IO_STANDARD='SB_LVCMOS'))]
connectors = [(connector pin 0 1=>F4), (connector pin 1 1=>E5), (connector pin 2 1=>E4), (connector pin 3 1=>F2)]
toolchain_program(products: BuildProducts, name: str) → None

Extract bitstream for fragment name from products and download it to a target.

class torii_boards.lattice.fomu_pvt.FomuPVTPlatform(*, toolchain: Literal['IceStorm', 'LSE-iCECube2', 'Synplify-iCECube2'] = 'IceStorm')
device = 'iCE40UP5K'
package = 'UWG30'
default_clk = 'clk48'
pretty_name = 'FOMU'
description = 'Im Tomu FPGA Lattice iCE40 UP5K FPGA Board'
resources = [(resource clk48 0 (pins i F4) (clock 48000000.0) (attrs GLOBAL=True IO_STANDARD='SB_LVCMOS')), (resource led 0 (pins-n o A5) (attrs IO_STANDARD='SB_LVCMOS')), (resource rgb_led 0 (subsignal r (pins-n o B5)) (subsignal g (pins-n o A5)) (subsignal b (pins-n o C5)) (attrs IO_STANDARD='SB_LVCMOS')), (resource usb 0 (subsignal d_p (pins io A1)) (subsignal d_n (pins io A2)) (subsignal pullup (pins o A4)) (attrs IO_STANDARD='SB_LVCMOS')), (resource spi_flash_1x 0 (subsignal cs (pins-n o C1)) (subsignal clk (pins o D1)) (subsignal copi (pins o F1)) (subsignal cipo (pins i E1)) (attrs IO_STANDARD='SB_LVCMOS')), (resource spi_flash_2x 0 (subsignal cs (pins-n o C1)) (subsignal clk (pins o D1)) (subsignal dq (pins io F1 E1)) (attrs IO_STANDARD='SB_LVCMOS')), (resource touch 0 (pins io E4)), (resource touch 1 (pins io D5)), (resource touch 2 (pins io E5)), (resource touch 3 (pins io F5))]
toolchain_program(products: BuildProducts, name: str) → None

Extract bitstream for fragment name from products and download it to a target.

class torii_boards.lattice.ice40_hx8k_b_evn.ICE40HX8KBEVNPlatform(*, toolchain: Literal['IceStorm', 'LSE-iCECube2', 'Synplify-iCECube2'] = 'IceStorm')
device = 'iCE40HX8K'
package = 'CT256'
default_clk = 'clk12'
pretty_name = 'ICE40HX8KEVN'
description = 'Lattice iCE40-HX8K Evaluation Board'
resources = [(resource clk12 0 (pins i J3) (clock 12000000.0) (attrs GLOBAL=True IO_STANDARD='SB_LVCMOS')), (resource led 0 (pins o C3) (attrs IO_STANDARD='SB_LVCMOS')), (resource led 1 (pins o B3) (attrs IO_STANDARD='SB_LVCMOS')), (resource led 2 (pins o C4) (attrs IO_STANDARD='SB_LVCMOS')), (resource led 3 (pins o C5) (attrs IO_STANDARD='SB_LVCMOS')), (resource led 4 (pins o A1) (attrs IO_STANDARD='SB_LVCMOS')), (resource led 5 (pins o A2) (attrs IO_STANDARD='SB_LVCMOS')), (resource led 6 (pins o B4) (attrs IO_STANDARD='SB_LVCMOS')), (resource led 7 (pins o B5) (attrs IO_STANDARD='SB_LVCMOS')), (resource uart 0 (subsignal rx (pins i B10)) (subsignal tx (pins o B12)) (subsignal rts (pins i B13)) (subsignal cts (pins o A15)) (subsignal dtr (pins i A16)) (subsignal dsr (pins o B14)) (subsignal dcd (pins o B15)) (attrs IO_STANDARD='SB_LVCMOS' PULLUP=1)), (resource spi_flash_1x 0 (subsignal cs (pins-n o R12)) (subsignal clk (pins o R11)) (subsignal copi (pins o P12)) (subsignal cipo (pins i P11)) (attrs IO_STANDARD='SB_LVCMOS')), (resource spi_flash_2x 0 (subsignal cs (pins-n o R12)) (subsignal clk (pins o R11)) (subsignal dq (pins io P12 P11)) (attrs IO_STANDARD='SB_LVCMOS'))]
connectors = [(connector j 1 1=>A16 3=>A15 4=>B15 5=>B13 6=>B14 9=>B12 10=>B11 11=>A11 12=>B10 13=>A10 14=>C9 17=>A9 18=>B9 19=>B8 20=>A7 21=>B7 22=>C7 25=>A6 26=>C6 27=>B6 28=>C5 29=>A5 30=>C4 33=>B5 34=>C3 35=>B4 36=>B3 37=>A2 38=>A1), (connector j 2 4=>R15 5=>P16 6=>P15 9=>N16 10=>M15 11=>M16 12=>L16 13=>K15 14=>K16 17=>K14 18=>J14 19=>G14 20=>F14 21=>J15 22=>H14 25=>H16 26=>G15 27=>G16 28=>F15 29=>F16 30=>E14 33=>E16 34=>D15 35=>D16 36=>D14 37=>C16 38=>B16), (connector j 3 1=>R16 3=>T15 4=>T16 5=>T13 6=>T14 9=>N12 10=>P13 11=>N10 12=>M11 13=>T11 14=>P10 17=>T10 18=>R10 19=>P8 20=>P9 21=>T9 22=>R9 25=>T7 26=>T8 27=>T6 28=>R6 29=>T5 30=>R5 33=>R3 34=>R4 35=>R2 36=>T3 37=>T1 38=>T2), (connector j 4 4=>R1 5=>P1 6=>P2 9=>N3 10=>N2 11=>M2 12=>M1 13=>L3 14=>L1 17=>K3 18=>K1 19=>J2 20=>J1 21=>H2 22=>J3 25=>G2 26=>H1 27=>F2 28=>G1 29=>E2 30=>F1 33=>D1 34=>D2 35=>C1 36=>C2 37=>B1 38=>B2)]
toolchain_program(products: BuildProducts, name: str) → None

Extract bitstream for fragment name from products and download it to a target.

class torii_boards.lattice.ice40_up5k_b_evn.ICE40UP5KBEVNPlatform(*, toolchain: Literal['IceStorm', 'LSE-iCECube2', 'Synplify-iCECube2'] = 'IceStorm')
device = 'iCE40UP5K'
package = 'SG48'
default_clk = 'clk12'
pretty_name = 'ICE40UP5KEVN'
description = 'Lattice iCE40-UP5K Evaluation Board'
resources = [(resource clk12 0 (pins i 35) (clock 12000000.0) (attrs GLOBAL=True IO_STANDARD='SB_LVCMOS')), (resource led 0 (pins-n o 39) (attrs IO_STANDARD='SB_LVCMOS')), (resource led 1 (pins-n o 40) (attrs IO_STANDARD='SB_LVCMOS')), (resource led 2 (pins-n o 41) (attrs IO_STANDARD='SB_LVCMOS')), (resource led_b 0 (pins-n o 39) (attrs IO_STANDARD='SB_LVCMOS')), (resource led_g 0 (pins-n o 40) (attrs IO_STANDARD='SB_LVCMOS')), (resource led_r 0 (pins-n o 41) (attrs IO_STANDARD='SB_LVCMOS')), (resource switch 0 (pins-n i 23) (attrs IO_STANDARD='SB_LVCMOS' PULLUP=1)), (resource switch 1 (pins-n i 25) (attrs IO_STANDARD='SB_LVCMOS' PULLUP=1)), (resource switch 2 (pins-n i 34) (attrs IO_STANDARD='SB_LVCMOS' PULLUP=1)), (resource switch 3 (pins-n i 43) (attrs IO_STANDARD='SB_LVCMOS' PULLUP=1)), (resource spi_flash_1x 0 (subsignal cs (pins-n o 16)) (subsignal clk (pins o 15)) (subsignal copi (pins o 14)) (subsignal cipo (pins i 17)) (attrs IO_STANDARD='SB_LVCMOS')), (resource spi_flash_2x 0 (subsignal cs (pins-n o 16)) (subsignal clk (pins o 15)) (subsignal dq (pins io 14 17)) (attrs IO_STANDARD='SB_LVCMOS'))]
connectors = [(connector aardvark 0 5=>14 7=>15 8=>17 9=>16), (connector pmod 0 1=>16 2=>14 3=>17 4=>15 7=>27 8=>26 9=>32 10=>31), (connector j 0 3=>39 4=>14 5=>40 6=>17 8=>15 9=>41 10=>16), (connector j 1 3=>23 5=>25 7=>26 8=>36 9=>27 10=>42 11=>32 12=>38 13=>31 14=>28 15=>37 16=>15 17=>34 19=>43), (connector j 2 2=>12 3=>3 4=>21 5=>3 6=>13 7=>48 8=>20 9=>45 10=>19 11=>47 12=>18 13=>44 14=>11 15=>46 16=>10 17=>2 18=>9 20=>6)]
toolchain_program(products: BuildProducts, name: str) → None

Extract bitstream for fragment name from products and download it to a target.

class torii_boards.lattice.icebreaker_bitsy.ICEBreakerBitsyPlatform(*, toolchain: Literal['IceStorm', 'LSE-iCECube2', 'Synplify-iCECube2'] = 'IceStorm')
device = 'iCE40UP5K'
package = 'SG48'
default_clk = 'clk12'
pretty_name = 'iCEBreaker Bitsy'
description = '1BitSquared iCEBreaker Bitsy Lattice iCE40-UP5K Development Board'
resources = [(resource clk12 0 (pins i 35) (clock 12000000.0) (attrs GLOBAL=True IO_STANDARD='SB_LVCMOS')), (resource usb 0 (subsignal d_p (pins io 42)) (subsignal d_n (pins io 38)) (subsignal pullup (pins o 37)) (attrs IO_STANDARD='SB_LVCMOS')), (resource spi_flash_1x 0 (subsignal cs (pins-n o 16)) (subsignal clk (pins o 15)) (subsignal copi (pins o 14)) (subsignal cipo (pins i 17)) (subsignal wp (pins-n o 18)) (subsignal hold (pins-n o 19)) (attrs IO_STANDARD='SB_LVCMOS')), (resource spi_flash_2x 0 (subsignal cs (pins-n o 16)) (subsignal clk (pins o 15)) (subsignal dq (pins io 14 17)) (attrs IO_STANDARD='SB_LVCMOS')), (resource spi_flash_4x 0 (subsignal cs (pins-n o 16)) (subsignal clk (pins o 15)) (subsignal dq (pins io 14 17 18 19)) (attrs IO_STANDARD='SB_LVCMOS')), (resource rgb_led 0 (subsignal r (pins-n o 39)) (subsignal g (pins-n o 40)) (subsignal b (pins-n o 41)) (attrs IO_STANDARD='SB_LVCMOS')), (resource led 0 (pins-n o 25) (attrs IO_STANDARD='SB_LVCMOS')), (resource led 1 (pins-n o 6) (attrs IO_STANDARD='SB_LVCMOS')), (resource led_r 0 (pins-n o 25) (attrs IO_STANDARD='SB_LVCMOS')), (resource led_g 0 (pins-n o 6) (attrs IO_STANDARD='SB_LVCMOS')), (resource button 0 (pins-n i 2) (attrs IO_STANDARD='SB_LVCMOS'))]
connectors = [(connector edge 0 0=>47 1=>44 2=>48 3=>45 4=>4 5=>3 6=>9 7=>10 8=>11 9=>12 10=>21 11=>13 12=>20 13=>25 14=>23 15=>27 16=>26 17=>28 18=>31 19=>32 20=>34 21=>36 22=>43 23=>46), (connector pmod 1 1=>edge_0:0 2=>edge_0:2 3=>edge_0:4 4=>edge_0:6 7=>edge_0:1 8=>edge_0:3 9=>edge_0:5 10=>edge_0:7), (connector pmod 2 1=>edge_0:22 2=>edge_0:19 3=>edge_0:16 4=>edge_0:17 7=>edge_0:21 8=>edge_0:18 9=>edge_0:15 10=>edge_0:20), (connector pmod 3 1=>edge_0:14 2=>edge_0:9 3=>edge_0:11 4=>edge_0:8 7=>edge_0:13 8=>edge_0:10 9=>edge_0:12 10=>edge_0:23)]
toolchain_program(products: BuildProducts, name: str, run_vid: str | None = None, run_pid: str | None = None, dfu_vid: str = '1d50', dfu_pid: str = '6146', reset: bool = True) → None

Extract bitstream for fragment name from products and download it to a target.

class torii_boards.lattice.icebreaker.ICEBreakerPlatform(*, toolchain: Literal['IceStorm', 'LSE-iCECube2', 'Synplify-iCECube2'] = 'IceStorm')
device = 'iCE40UP5K'
package = 'SG48'
default_clk = 'clk12'
pretty_name = 'iCEBreaker'
description = '1BitSquared iCEBreaker Lattice iCE40-UP5K Development Board'
resources = [(resource clk12 0 (pins i 35) (clock 12000000.0) (attrs GLOBAL=True IO_STANDARD='SB_LVCMOS')), (resource led 0 (pins-n o 11) (attrs IO_STANDARD='SB_LVCMOS')), (resource led 1 (pins-n o 37) (attrs IO_STANDARD='SB_LVCMOS')), (resource led_r 0 (pins-n o 11) (attrs IO_STANDARD='SB_LVCMOS')), (resource led_g 0 (pins-n o 37) (attrs IO_STANDARD='SB_LVCMOS')), (resource button 0 (pins-n i 10) (attrs IO_STANDARD='SB_LVCMOS')), (resource uart 0 (subsignal rx (pins i 6)) (subsignal tx (pins o 9)) (attrs IO_STANDARD='SB_LVTTL' PULLUP=1)), (resource spi_flash_1x 0 (subsignal cs (pins-n o 16)) (subsignal clk (pins o 15)) (subsignal copi (pins o 14)) (subsignal cipo (pins i 17)) (subsignal wp (pins-n o 12)) (subsignal hold (pins-n o 13)) (attrs IO_STANDARD='SB_LVCMOS')), (resource spi_flash_2x 0 (subsignal cs (pins-n o 16)) (subsignal clk (pins o 15)) (subsignal dq (pins io 14 17)) (attrs IO_STANDARD='SB_LVCMOS')), (resource spi_flash_4x 0 (subsignal cs (pins-n o 16)) (subsignal clk (pins o 15)) (subsignal dq (pins io 14 17 12 13)) (attrs IO_STANDARD='SB_LVCMOS'))]
connectors = [(connector pmod 0 1=>4 2=>2 3=>47 4=>45 7=>3 8=>48 9=>46 10=>44), (connector pmod 1 1=>43 2=>38 3=>34 4=>31 7=>42 8=>36 9=>32 10=>28), (connector pmod 2 1=>27 2=>25 3=>21 4=>19 7=>26 8=>23 9=>20 10=>18)]
break_off_pmod = [(resource led 2 (pins o pmod_2:7) (attrs IO_STANDARD='SB_LVCMOS')), (resource led 3 (pins o pmod_2:1) (attrs IO_STANDARD='SB_LVCMOS')), (resource led 4 (pins o pmod_2:2) (attrs IO_STANDARD='SB_LVCMOS')), (resource led 5 (pins o pmod_2:8) (attrs IO_STANDARD='SB_LVCMOS')), (resource led 6 (pins o pmod_2:3) (attrs IO_STANDARD='SB_LVCMOS')), (resource led_r 1 (pins o pmod_2:7) (attrs IO_STANDARD='SB_LVCMOS')), (resource led_g 1 (pins o pmod_2:1) (attrs IO_STANDARD='SB_LVCMOS')), (resource led_g 2 (pins o pmod_2:2) (attrs IO_STANDARD='SB_LVCMOS')), (resource led_g 3 (pins o pmod_2:8) (attrs IO_STANDARD='SB_LVCMOS')), (resource led_g 4 (pins o pmod_2:3) (attrs IO_STANDARD='SB_LVCMOS')), (resource button 1 (pins i pmod_2:9) (attrs IO_STANDARD='SB_LVCMOS')), (resource button 2 (pins i pmod_2:4) (attrs IO_STANDARD='SB_LVCMOS')), (resource button 3 (pins i pmod_2:10) (attrs IO_STANDARD='SB_LVCMOS'))]
toolchain_program(products: BuildProducts, name: str) → None

Extract bitstream for fragment name from products and download it to a target.

class torii_boards.lattice.icestick.ICEStickPlatform(*, toolchain: Literal['IceStorm', 'LSE-iCECube2', 'Synplify-iCECube2'] = 'IceStorm')
device = 'iCE40HX1K'
package = 'TQ144'
default_clk = 'clk12'
pretty_name = 'iCEstick'
description = 'Lattice iCEstick iCE40-HX1K Evaluation Kit'
resources = [(resource clk12 0 (pins i 21) (clock 12000000.0) (attrs GLOBAL=True IO_STANDARD='SB_LVCMOS')), (resource led 0 (pins o 99) (attrs IO_STANDARD='SB_LVCMOS')), (resource led 1 (pins o 98) (attrs IO_STANDARD='SB_LVCMOS')), (resource led 2 (pins o 97) (attrs IO_STANDARD='SB_LVCMOS')), (resource led 3 (pins o 96) (attrs IO_STANDARD='SB_LVCMOS')), (resource led 4 (pins o 95) (attrs IO_STANDARD='SB_LVCMOS')), (resource uart 0 (subsignal rx (pins i 9)) (subsignal tx (pins o 8)) (subsignal rts (pins i 7)) (subsignal cts (pins o 4)) (subsignal dtr (pins i 3)) (subsignal dsr (pins o 2)) (subsignal dcd (pins o 1)) (attrs IO_STANDARD='SB_LVTTL' PULLUP=1)), (resource irda 0 (subsignal rx (pins i 106)) (subsignal tx (pins o 105)) (subsignal en (pins-n o 107)) (attrs IO_STANDARD='SB_LVCMOS')), (resource spi_flash_1x 0 (subsignal cs (pins-n o 71)) (subsignal clk (pins o 70)) (subsignal copi (pins o 67)) (subsignal cipo (pins i 68)) (attrs IO_STANDARD='SB_LVCMOS')), (resource spi_flash_2x 0 (subsignal cs (pins-n o 71)) (subsignal clk (pins o 70)) (subsignal dq (pins io 67 68)) (attrs IO_STANDARD='SB_LVCMOS'))]
connectors = [(connector pmod 0 1=>78 2=>79 3=>80 4=>81 7=>87 8=>88 9=>90 10=>91), (connector j 1 3=>112 4=>113 5=>114 6=>115 7=>116 8=>117 9=>118 10=>119), (connector j 3 3=>62 4=>61 5=>60 6=>56 7=>48 8=>47 9=>45 10=>44)]
toolchain_program(products: BuildProducts, name: str) → None

Extract bitstream for fragment name from products and download it to a target.

class torii_boards.lattice.icesugar_nano.ICESugarNanoPlatform(*, toolchain: Literal['IceStorm', 'LSE-iCECube2', 'Synplify-iCECube2'] = 'IceStorm')
device = 'iCE40LP1K'
package = 'CM36'
default_clk = 'clk12'
pretty_name = 'iCESugar-nano'
description = 'iCESugar-nano Lattice iCE40-LP1K Development Board'
resources = [(resource clk12 0 (pins i D1) (clock 12000000.0) (attrs GLOBAL=True IO_STANDARD='LVCMOS33')), (resource led 0 (pins o B6) (attrs IO_STANDARD='LVCMOS33')), (resource uart 0 (subsignal rx (pins i A3)) (subsignal tx (pins o B3)) (attrs IO_STANDARD='LVTTL33' PULLUP=1)), (resource spi_flash_1x 0 (subsignal cs (pins-n o D5)) (subsignal clk (pins o E5)) (subsignal copi (pins o E4)) (subsignal cipo (pins i F5)) (attrs IO_STANDARD='LVCMOS33')), (resource spi_flash_2x 0 (subsignal cs (pins-n o D5)) (subsignal clk (pins o E5)) (subsignal dq (pins io E4 F5)) (attrs IO_STANDARD='LVCMOS33'))]
connectors = [(connector pmod 0 1=>E2 2=>D1 3=>B1 4=>A1), (connector pmod 1 1=>B3 2=>A3 3=>B6 4=>C5), (connector pmod 2 1=>B4 2=>B5 3=>E1 4=>B1 7=>C6 8=>E3 9=>C2 10=>A1)]
toolchain_program(products: BuildProducts, name: str) → None

Extract bitstream for fragment name from products and download it to a target.

class torii_boards.lattice.logicbone.LogicbonePlatform(*, toolchain: Literal['Trellis', 'Diamond'] = 'Trellis')
name = 'Logicbone'
device = 'LFE5UM5G-45F'
package = 'BG381'
speed = '8'
default_clk = 'refclk'
pretty_name = 'Logicbone'
description = 'Logicbone Lattice ECP5-5G-45F Development Board'
resources = [(resource refclk 0 (pins i M19) (clock 25000000.0) (attrs IO_TYPE='LVCMOS18')), (resource serdes 0 (subsignal rx (diffpairs io (p Y5) (n Y6))) (subsignal tx (diffpairs io (p W4) (n W5)))), (resource serdes 1 (subsignal rx (diffpairs io (p Y8) (n Y7))) (subsignal tx (diffpairs io (p W8) (n W9)))), (resource usb 0 (subsignal d_p (pins io B12)) (subsignal d_n (pins io C12)) (subsignal pullup (pins o C16)) (attrs IO_TYPE='LVCMOS33')), (resource usb 1 (subsignal d_p (pins io R1)) (subsignal d_n (pins io T1)) (subsignal pullup (pins o T2)) (attrs IO_TYPE='LVCMOS33')), (resource led 0 (pins-n o D16) (attrs IO_TYPE='LVCMOS33')), (resource led 1 (pins-n o C15) (attrs IO_TYPE='LVCMOS33')), (resource led 2 (pins-n o C13) (attrs IO_TYPE='LVCMOS33')), (resource led 3 (pins-n o B13) (attrs IO_TYPE='LVCMOS33')), (resource button 0 (pins-n i U2) (attrs IO_TYPE='LVCMOS33')), (resource spi_flash_1x 0 (subsignal cs (pins-n o R2)) (subsignal clk (pins o U3)) (subsignal copi (pins o W2)) (subsignal cipo (pins i V2)) (subsignal wp (pins-n o Y2)) (subsignal hold (pins-n o W1)) (attrs IO_TYPE='LVCMOS33')), (resource spi_flash_2x 0 (subsignal cs (pins-n o R2)) (subsignal clk (pins o U3)) (subsignal dq (pins io W2 V2)) (attrs IO_TYPE='LVCMOS33')), (resource spi_flash_4x 0 (subsignal cs (pins-n o R2)) (subsignal clk (pins o U3)) (subsignal dq (pins io W2 V2 Y2 W1)) (attrs IO_TYPE='LVCMOS33')), (resource sd_card_1bit 0 (subsignal cd (pins i D14)) (subsignal clk (pins o E11)) (subsignal cmd (pins o D15)) (subsignal dat (pins io D13)) (subsignal ecd (pins i E13)) (attrs IO_TYPE='LVCMOS33')), (resource sd_card_4bit 0 (subsignal cd (pins i D14)) (subsignal clk (pins o E11)) (subsignal cmd (pins o D15)) (subsignal dat (pins io D13 E13 E15 E13)) (attrs IO_TYPE='LVCMOS33')), (resource sd_card_spi 0 (subsignal cd (pins i D14)) (subsignal cs (pins-n io E13)) (subsignal clk (pins o E11)) (subsignal copi (pins o D15)) (subsignal cipo (pins i D13)) (attrs IO_TYPE='LVCMOS33')), (resource eth_clk125 0 (pins i A19) (clock 125000000.0) (attrs IO_TYPE='LVCMOS33')), (resource eth_rgmii 0 (subsignal int (pins i B20)) (subsignal mdc (pins o D12)) (subsignal mdio (pins io B19)) (subsignal tx_clk (pins o A15)) (subsignal tx_ctl (pins o B15)) (subsignal tx_data (pins o A12 A13 C14 A14)) (subsignal rx_clk (pins i B18)) (subsignal rx_ctl (pins i A18)) (subsignal rx_data (pins i B17 A17 B16 A16)) (attrs IO_TYPE='LVCMOS33')), (resource ddr3 0 (subsignal rst (pins-n o P1)) (subsignal clk (diffpairs o (p M4) (n N5)) (attrs IO_TYPE='LVDS')) (subsignal clk_en (pins o K4)) (subsignal cs (pins-n o M3)) (subsignal we (pins-n o E4)) (subsignal ras (pins-n o L1)) (subsignal cas (pins-n o M1)) (subsignal a (pins o D5 F4 B3 F3 E5 C3 C4 A5 A3 B5 G3 F5 D2 A4 D3 E3)) (subsignal ba (pins o B4 H5 N2)) (subsignal dqs (diffpairs io (p K2 H4) (n J1 G5)) (attrs IO_TYPE='LVDS')) (subsignal dq (pins io G2 K1 F1 K3 H2 J3 G1 H1 B1 E1 A2 F2 C1 E2 C2 D1)) (subsignal dm (pins o L4 J5)) (subsignal odt (pins o C5)) (attrs IO_TYPE='SSTL135_I'))]
connectors = [(connector P8 0 3=>C20 4=>D19 5=>D20 6=>E19 7=>E20 8=>F19 9=>F20 10=>G20 23=>G19 24=>H20 25=>J20 26=>K20 27=>C18 28=>D17 29=>D18 30=>E17 31=>E18 32=>F18 33=>F17 34=>G18 35=>E16 36=>F16 37=>G16 38=>H16 39=>J17 40=>J16 41=>H18 42=>H17 43=>J19 44=>K19 45=>J18 46=>K18), (connector P9 0 12=>A11 13=>B11 14=>A10 15=>C10 16=>A9 17=>B9 18=>C11 19=>A8 22=>D9 23=>C8 24=>B8 25=>A7 26=>A6 27=>B6 28=>D8 29=>C7 30=>D7 31=>C6 32=>D6 42=>B10 43=>E10)]
toolchain_prepare(fragment: Fragment, name: str, **kwargs) → BuildPlan

Convert the fragment and constraints recorded in this Platform into a BuildPlan.

toolchain_program(products: BuildProducts, name: str) → None

Extract bitstream for fragment name from products and download it to a target.

class torii_boards.lattice.logicbone.Logicbone85FPlatform(*, toolchain: Literal['Trellis', 'Diamond'] = 'Trellis')
name = 'Logicbone (85F Variant)'
device = 'LFE5UM5G-85F'
class torii_boards.lattice.machxo3_sk.MachXO3SKPlatform
device = 'LCMXO3LF-6900C'
package = 'BG256'
speed = '5'
default_clk = 'clk12'
pretty_name = 'MachXO3SK'
description = 'Lattice MachXO3LF Starter Kit'
resources = [(resource clk12 0 (pins i C8) (clock 12000000.0) (attrs IO_TYPE='LVCMOS33')), (resource uart 0 (subsignal rx (pins i A11)) (subsignal tx (pins o C11)) (subsignal rts (pins i F10)) (subsignal cts (pins o D11)) (subsignal dtr (pins i B11)) (subsignal dsr (pins o A12)) (subsignal dcd (pins o B13)) (subsignal ri (pins o A14)) (attrs IO_TYPE='LVCMOS33')), (resource led 0 (pins-n o H11) (attrs IO_TYPE='LVCMOS33')), (resource led 1 (pins-n o J13) (attrs IO_TYPE='LVCMOS33')), (resource led 2 (pins-n o J11) (attrs IO_TYPE='LVCMOS33')), (resource led 3 (pins-n o L12) (attrs IO_TYPE='LVCMOS33')), (resource led 4 (pins-n o K11) (attrs IO_TYPE='LVCMOS33')), (resource led 5 (pins-n o L13) (attrs IO_TYPE='LVCMOS33')), (resource led 6 (pins-n o N15) (attrs IO_TYPE='LVCMOS33')), (resource led 7 (pins-n o P16) (attrs IO_TYPE='LVCMOS33')), (resource button 0 (pins-n i B3) (attrs IO_TYPE='LVCMOS33')), (resource switch 0 (pins-n i N2) (attrs IO_TYPE='LVCMOS33')), (resource switch 1 (pins-n i P1) (attrs IO_TYPE='LVCMOS33')), (resource switch 2 (pins-n i M3) (attrs IO_TYPE='LVCMOS33')), (resource switch 3 (pins-n i N1) (attrs IO_TYPE='LVCMOS33')), (resource spi_flash_1x 0 (subsignal cs (pins-n o R5)) (subsignal clk (pins o P6)) (subsignal copi (pins o T13)) (subsignal cipo (pins i T6)) (attrs IO_TYPE='LVCMOS33')), (resource spi_flash_2x 0 (subsignal cs (pins-n o R5)) (subsignal clk (pins o P6)) (subsignal dq (pins io T13 T6)) (attrs IO_TYPE='LVCMOS33'))]
connectors = [(connector j 3 3=>A13 4=>C13 5=>F8 6=>B12 7=>C12 8=>E11 9=>E10 10=>D10 13=>F9 14=>C10 15=>E8 16=>E9 17=>E7 18=>D8 19=>D7 20=>C7 23=>C5 24=>D6 25=>E6 26=>C4 27=>A10 28=>F7 29=>D9 30=>B9 33=>B6 34=>B7 35=>B5 36=>A5 37=>B4 38=>A4 40=>A3), (connector j 4 3=>K12 4=>K13 5=>M14 6=>N14 7=>L14 8=>N16 9=>M15 10=>M16 13=>L15 14=>L16 15=>K14 16=>K16 17=>K15 18=>J14 19=>H14 20=>J15 23=>J16 24=>H15 25=>H16 26=>G15 27=>G16 28=>F15 29=>F16 30=>E15 33=>E16 34=>E14 35=>D16 36=>C15 37=>D14 38=>F14 39=>G14 40=>B16), (connector j 6 3=>T12 4=>T14 5=>R11 6=>R13 7=>T11 8=>M11 9=>P11 10=>N10 13=>T10 14=>P10 15=>R9 16=>R10 17=>T9 18=>N9 19=>P9 20=>M8 23=>T8 24=>L8 25=>P8 26=>M6 27=>R7 28=>R8 29=>P7 30=>T7 33=>L7 34=>R6 35=>N6 36=>T5 37=>R4 38=>P4 39=>T3 40=>T4), (connector j 8 3=>H6 4=>N3 5=>M2 6=>M1 7=>L2 8=>L1 9=>L3 10=>L5 13=>K4 14=>J1 15=>K1 16=>J2 17=>J3 18=>H3 19=>H2 20=>H1 23=>G2 24=>G1 25=>F2 26=>F1 27=>E2 28=>E1 29=>D2 30=>D1 33=>C2 34=>C1 35=>G3 36=>B1 37=>D3 38=>E3 39=>F3 40=>F5)]
toolchain_program(products: BuildProducts, name: str) → None

Extract bitstream for fragment name from products and download it to a target.

class torii_boards.lattice.nandland_go.NandlandGoPlatform(*, toolchain: Literal['IceStorm', 'LSE-iCECube2', 'Synplify-iCECube2'] = 'IceStorm')
device = 'iCE40HX1K'
package = 'VQ100'
default_clk = 'clk25'
pretty_name = 'Nandland Go'
description = 'Nandland Go Lattice iCE40-HX1K Development Board'
resources = [(resource clk25 0 (pins i 15) (clock 25000000.0)), (resource led 0 (pins o 56)), (resource led 1 (pins o 57)), (resource led 2 (pins o 59)), (resource led 3 (pins o 60)), (resource button 0 (pins i 53)), (resource button 1 (pins i 51)), (resource button 2 (pins i 54)), (resource button 3 (pins i 52)), (resource display_7seg 0 (subsignal a (pins-n o 3)) (subsignal b (pins-n o 4)) (subsignal c (pins-n o 93)) (subsignal d (pins-n o 91)) (subsignal e (pins-n o 90)) (subsignal f (pins-n o 1)) (subsignal g (pins-n o 2))), (resource display_7seg 1 (subsignal a (pins-n o 100)) (subsignal b (pins-n o 99)) (subsignal c (pins-n o 97)) (subsignal d (pins-n o 95)) (subsignal e (pins-n o 94)) (subsignal f (pins-n o 8)) (subsignal g (pins-n o 96))), (resource uart 0 (subsignal rx (pins i 73)) (subsignal tx (pins o 74))), (resource spi_flash_1x 0 (subsignal cs (pins-n o 49)) (subsignal clk (pins o 48)) (subsignal copi (pins o 45)) (subsignal cipo (pins i 46))), (resource spi_flash_2x 0 (subsignal cs (pins-n o 49)) (subsignal clk (pins o 48)) (subsignal dq (pins io 45 46))), (resource vga 0 (subsignal r (pins o 36 37 40)) (subsignal g (pins o 29 30 33)) (subsignal b (pins o 28 41 42)) (subsignal hs (pins o 26)) (subsignal vs (pins o 27)))]
connectors = [(connector pmod 0 1=>65 2=>64 3=>63 4=>62 7=>78 8=>79 9=>80 10=>81)]
toolchain_program(products: BuildProducts, name: str) → None

Extract bitstream for fragment name from products and download it to a target.

class torii_boards.lattice.orangecrab_r0_1.OrangeCrabR0_1Platform(*, toolchain: Literal['Trellis', 'Diamond'] = 'Trellis')
device = 'LFE5U-25F'
package = 'MG285'
speed = '8'
default_clk = 'clk'
pretty_name = 'OrangeCrab R0.1'
description = 'OrangeCrab R0.1 Lattice ECP5-25F Development Board'
resources = [(resource clk 0 (pins i A9) (clock 48000000.0) (attrs IO_TYPE='LVCMOS33')), (resource program 0 (pins-n o R16) (attrs IO_TYPE='LVCMOS33')), (resource rgb_led 0 (subsignal r (pins-n o V17)) (subsignal g (pins-n o T17)) (subsignal b (pins-n o J3)) (attrs IO_TYPE='LVCMOS33')), (resource spi_flash_1x 0 (subsignal cs (pins-n o U17)) (subsignal clk (pins o U16)) (subsignal copi (pins o U18)) (subsignal cipo (pins i T18)) (subsignal wp (pins-n o R18)) (subsignal hold (pins-n o N18)) (attrs IO_TYPE='LVCMOS33')), (resource spi_flash_2x 0 (subsignal cs (pins-n o U17)) (subsignal clk (pins o U16)) (subsignal dq (pins io U18 T18)) (attrs IO_TYPE='LVCMOS33')), (resource spi_flash_4x 0 (subsignal cs (pins-n o U17)) (subsignal clk (pins o U16)) (subsignal dq (pins io U18 T18 R18 N18)) (attrs IO_TYPE='LVCMOS33')), (resource ddr3 0 (subsignal rst (pins-n o B1)) (subsignal clk (diffpairs o (p J18) (n K18)) (attrs IO_TYPE='SSTL135D_I')) (subsignal clk_en (pins o D6)) (subsignal cs (pins-n o A12)) (subsignal we (pins-n o B12)) (subsignal ras (pins-n o C12)) (subsignal cas (pins-n o D13)) (subsignal a (pins o A4 D2 C3 C7 D3 D4 D1 B2 C1 A2 A7 C2 C4)) (subsignal ba (pins o B6 B7 A6)) (subsignal dqs (diffpairs io (p G18 H17) (n B15 A16)) (attrs IO_TYPE='SSTL135D_I' TERMINATION='OFF' DIFFRESISTOR='100')) (subsignal dq (pins io F17 F16 G15 F15 J16 C18 H16 F18 C17 D15 B17 C16 A15 B13 A17 A13) (attrs TERMINATION='75')) (subsignal dm (pins o G16 D16)) (subsignal odt (pins o C13)) (attrs IO_TYPE='SSTL135_I' SLEWRATE='FAST')), (resource ddr3_pseudo_power 0 (subsignal vcc_virtual (pins-n o A3 B18 C6 C15 D17 D18 K15 K16 K17)) (subsignal gnd_virtual (pins o L15 L16 L18)) (attrs IO_TYPE='SSTL135_II' SLEWRATE='FAST')), (resource sd_card_1bit 0 (subsignal cd (pins i L1)) (subsignal clk (pins o K1)) (subsignal cmd (pins o K2)) (subsignal dat (pins io J1)) (subsignal ecd (pins i M1)) (attrs IO_TYPE='LVCMOS33' SLEWRATE='FAST')), (resource sd_card_4bit 0 (subsignal cd (pins i L1)) (subsignal clk (pins o K1)) (subsignal cmd (pins o K2)) (subsignal dat (pins io J1 K3 L3 M1)) (attrs IO_TYPE='LVCMOS33' SLEWRATE='FAST')), (resource sd_card_spi 0 (subsignal cd (pins i L1)) (subsignal cs (pins-n io M1)) (subsignal clk (pins o K1)) (subsignal copi (pins o K2)) (subsignal cipo (pins i J1)) (attrs IO_TYPE='LVCMOS33' SLEWRATE='FAST')), (resource usb 0 (subsignal d_p (pins io N1)) (subsignal d_n (pins io M2)) (subsignal pullup (pins o N2)) (attrs IO_TYPE='LVCMOS33'))]
connectors = [(connector io 0 0=>N17 1=>M18 5=>B10 6=>B9 9=>C8 10=>B8 11=>A8 12=>H2 13=>J2 cipo=>N15 copi=>N16 sck=>R17 scl=>C9 sda=>C10), (connector mcu 0 0=>A10 1=>C11 2=>A11 3=>B11)]
property required_tools: List[str]
property command_templates: List[str]
toolchain_prepare(fragment: Fragment, name: str, **kwargs) → BuildPlan

Convert the fragment and constraints recorded in this Platform into a BuildPlan.

toolchain_program(products: BuildProducts, name: str) → None

Extract bitstream for fragment name from products and download it to a target.

class torii_boards.lattice.orangecrab_r0_2.OrangeCrabR0_2Platform(*, toolchain: Literal['Trellis', 'Diamond'] = 'Trellis')
device = 'LFE5U-25F'
package = 'MG285'
speed = '8'
default_clk = 'clk'
pretty_name = 'OrangeCrab R0.2'
description = 'OrangeCrab R0.2 Lattice ECP5-25F Development Board'
resources = [(resource clk 0 (pins i A9) (clock 48000000.0) (attrs IO_TYPE='LVCMOS33')), (resource program 0 (pins-n o V17) (attrs IO_TYPE='LVCMOS33')), (resource rgb_led 0 (subsignal r (pins-n o K4)) (subsignal g (pins-n o M3)) (subsignal b (pins-n o J3)) (attrs IO_TYPE='LVCMOS33')), (resource button 0 (pins-n i J17) (attrs IO_TYPE='SSTL135_I')), (resource spi_flash_1x 0 (subsignal cs (pins-n o U17)) (subsignal clk (pins o U16)) (subsignal copi (pins o U18)) (subsignal cipo (pins i T18)) (subsignal wp (pins-n o R18)) (subsignal hold (pins-n o N18)) (attrs IO_TYPE='LVCMOS33')), (resource spi_flash_2x 0 (subsignal cs (pins-n o U17)) (subsignal clk (pins o U16)) (subsignal dq (pins io U18 T18)) (attrs IO_TYPE='LVCMOS33')), (resource spi_flash_4x 0 (subsignal cs (pins-n o U17)) (subsignal clk (pins o U16)) (subsignal dq (pins io U18 T18 R18 N18)) (attrs IO_TYPE='LVCMOS33')), (resource ddr3 0 (subsignal rst (pins-n o L18)) (subsignal clk (diffpairs o (p J18) (n K18)) (attrs IO_TYPE='SSTL135D_I')) (subsignal clk_en (pins o D18)) (subsignal cs (pins-n o A12)) (subsignal we (pins-n o B12)) (subsignal ras (pins-n o C12)) (subsignal cas (pins-n o D13)) (subsignal a (pins o C4 D2 D3 A3 A4 D4 C3 B2 B1 D1 A7 C2 B6 C1 A2 C7)) (subsignal ba (pins o P5 N3 M3)) (subsignal dqs (diffpairs io (p G18 H17) (n B15 A16)) (attrs IO_TYPE='SSTL135D_I' TERMINATION='OFF' DIFFRESISTOR='100')) (subsignal dq (pins io C17 D15 B17 C16 A15 B13 A17 A13 F17 F16 G15 F15 J16 C18 H16 F18) (attrs TERMINATION='75')) (subsignal dm (pins o G16 D16)) (subsignal odt (pins o C13)) (attrs IO_TYPE='SSTL135_I' SLEWRATE='FAST')), (resource ddr3_pseudo_power 0 (subsignal vcc_virtual (pins-n o K16 D17 K15 K17 B18 C6)) (subsignal gnd_virtual (pins o L15 L16)) (attrs IO_TYPE='SSTL135_II' SLEWRATE='FAST')), (resource adc 0 (subsignal ctrl (pins o G1 F1)) (subsignal mux (pins o F4 F3 F2 H1)) (subsignal sense (diffpairs i (p H3) (n G3)) (attrs IO_TYPE='LVCMOS33D')) (attrs IO_TYPE='LVCMOS33')), (resource sd_card_1bit 0 (subsignal cd (pins i L1)) (subsignal clk (pins o K1)) (subsignal cmd (pins o K2)) (subsignal dat (pins io J1)) (subsignal ecd (pins i M1)) (attrs IO_TYPE='LVCMOS33' SLEWRATE='FAST')), (resource sd_card_4bit 0 (subsignal cd (pins i L1)) (subsignal clk (pins o K1)) (subsignal cmd (pins o K2)) (subsignal dat (pins io J1 K3 L3 M1)) (attrs IO_TYPE='LVCMOS33' SLEWRATE='FAST')), (resource sd_card_spi 0 (subsignal cd (pins i L1)) (subsignal cs (pins-n io M1)) (subsignal clk (pins o K1)) (subsignal copi (pins o K2)) (subsignal cipo (pins i J1)) (attrs IO_TYPE='LVCMOS33' SLEWRATE='FAST')), (resource usb 0 (subsignal d_p (pins io N1)) (subsignal d_n (pins io M2)) (subsignal pullup (pins o N2)) (attrs IO_TYPE='LVCMOS33'))]
connectors = [(connector io 0 0=>N17 1=>M18 5=>B10 6=>B9 9=>C8 10=>B8 11=>A8 12=>H2 13=>J2 a0=>L4 a1=>N3 a2=>N4 a3=>H4 a4=>G4 cipo=>N15 copi=>N16 sck=>R17 scl=>C9 sda=>C10)]
property required_tools: List[str]
property command_templates: List[str]
toolchain_prepare(fragment: Fragment, name: str, **kwargs) → BuildPlan

Convert the fragment and constraints recorded in this Platform into a BuildPlan.

toolchain_program(products: BuildProducts, name: str) → None

Extract bitstream for fragment name from products and download it to a target.

class torii_boards.lattice.orangecrab_r0_2.OrangeCrabR0_2_25FPlatform(*, toolchain: Literal['Trellis', 'Diamond'] = 'Trellis')
pretty_name = 'OrangeCrab R0.2 25F'
description = 'OrangeCrab R0.2 Lattice ECP5-25F Development Board'
class torii_boards.lattice.orangecrab_r0_2.OrangeCrabR0_2_85FPlatform(*, toolchain: Literal['Trellis', 'Diamond'] = 'Trellis')
device = 'LFE5U-85F'
pretty_name = 'OrangeCrab R0.2 85F'
description = 'OrangeCrab R0.2 Lattice ECP5-85F Development Board'
class torii_boards.lattice.supercon19badge.Supercon19BadgePlatform(*, toolchain: Literal['Trellis', 'Diamond'] = 'Trellis')
device = 'LFE5U-45F'
package = 'BG381'
speed = '8'
default_clk = 'clk8'
pretty_name = 'Supercon 19 Badge'
description = 'Lattice ECP5-45F Based Hackaday Supercon 2019 Badge'
led_cathode_mappings = [{'b': 2, 'g': 1, 'r': 0}, {'b': 0, 'g': 1, 'r': 2}, {'b': 2, 'g': 1, 'r': 0}, {'b': 0, 'g': 1, 'r': 2}, {'b': 2, 'g': 1, 'r': 0}, {'b': 0, 'g': 1, 'r': 2}, {'b': 1, 'g': 0, 'r': 2}, {'b': 2, 'g': 1, 'r': 0}, {'b': 2, 'g': 1, 'r': 0}, {'b': 0, 'g': 1, 'r': 2}, {'b': 2, 'g': 0, 'r': 1}]
resources = [(resource clk8 0 (pins io U18) (clock 8000000.0) (attrs IO_TYPE='LVCMOS33')), (resource program 0 (pins-n io R1) (attrs IO_TYPE='LVCMOS33')), (resource led 0 (pins o E3) (attrs IO_TYPE='LVCMOS33')), (resource led 1 (pins o D3) (attrs IO_TYPE='LVCMOS33')), (resource led 2 (pins o C3) (attrs IO_TYPE='LVCMOS33')), (resource led 3 (pins o C4) (attrs IO_TYPE='LVCMOS33')), (resource led 4 (pins o C2) (attrs IO_TYPE='LVCMOS33')), (resource led 5 (pins o B1) (attrs IO_TYPE='LVCMOS33')), (resource led 6 (pins o B20) (attrs IO_TYPE='LVCMOS33')), (resource led 7 (pins o B19) (attrs IO_TYPE='LVCMOS33')), (resource led 8 (pins o A18) (attrs IO_TYPE='LVCMOS33')), (resource led 9 (pins o K20) (attrs IO_TYPE='LVCMOS33')), (resource led 10 (pins o K19) (attrs IO_TYPE='LVCMOS33')), (resource led_cathodes 0 (pins io P19 L18 K18) (attrs IO_TYPE='LVCMOS33')), (resource uart 0 (subsignal rx (pins i U2)) (subsignal tx (pins o U1)) (attrs IO_TYPE='LVCMOS33')), (resource usb 0 (subsignal d_p (pins io F3)) (subsignal d_n (pins io G3)) (subsignal pullup (pins o E4)) (subsignal vbus_valid (pins i F4)) (attrs IO_TYPE='LVCMOS33')), (resource button 0 (pins i G2) (attrs IO_TYPE='LVCMOS33' PULLMODE='UP')), (resource button 1 (pins i F2) (attrs IO_TYPE='LVCMOS33' PULLMODE='UP')), (resource button 2 (pins i F1) (attrs IO_TYPE='LVCMOS33' PULLMODE='UP')), (resource button 3 (pins i C1) (attrs IO_TYPE='LVCMOS33' PULLMODE='UP')), (resource button 4 (pins i E1) (attrs IO_TYPE='LVCMOS33' PULLMODE='UP')), (resource button 5 (pins i D2) (attrs IO_TYPE='LVCMOS33' PULLMODE='UP')), (resource button 6 (pins i D1) (attrs IO_TYPE='LVCMOS33' PULLMODE='UP')), (resource button 7 (pins i E2) (attrs IO_TYPE='LVCMOS33' PULLMODE='UP')), (resource keypad 0 (subsignal left (pins i G2)) (subsignal right (pins i F2)) (subsignal up (pins i F1)) (subsignal down (pins i C1)) (subsignal start (pins i E1)) (subsignal select (pins i D2)) (subsignal a (pins i D1)) (subsignal b (pins i E2)) (attrs IO_TYPE='LVCMOS33' PULLMODE='UP')), (resource hdmi 0 (subsignal clk (diffpairs-n io (p P20) (n R20)) (attrs IO_TYPE='TMDS_33')) (subsignal d (diffpairs io (p N19 L20 L16) (n N20 M20 L17)) (attrs IO_TYPE='TMDS_33')) (subsignal hpd (pins-n io R18) (attrs IO_TYPE='LVCMOS33')) (subsignal hdmi_heac_p (pins-n io T19) (attrs IO_TYPE='LVCMOS33')) (attrs DRIVE='4')), (resource lcd 0 (subsignal db (pins io J3 H1 K4 J1 K3 K2 L4 K1 L3 L2 M4 L1 M3 M1 N4 N2 N3 N1)) (subsignal rd (pins io P2)) (subsignal wr (pins io P4)) (subsignal rs (pins io P1)) (subsignal cs (pins io P3)) (subsignal id (pins io J4)) (subsignal rst (pins io H2)) (subsignal fmark (pins io G1)) (subsignal blen (pins io P5)) (attrs IO_TYPE='LVCMOS33')), (resource spi_flash 0 (subsignal cs (pins-n io R2)) (subsignal copi (pins io W2)) (subsignal cipo (pins io V2)) (subsignal wp (pins io Y2)) (subsignal hold (pins io W1)) (attrs IO_TYPE='LVCMOS33')), (resource spi_flash_4x 0 (subsignal cs (pins-n io R2)) (subsignal dq (pins io W2 V2 Y2 W1)) (attrs IO_TYPE='LVCMOS33')), (resource spi_psram_4x 0 (subsignal cs (pins-n io D20)) (subsignal clk (pins io E20)) (subsignal dq (pins io E19 D19 C20 F19) (attrs PULLMODE='UP')) (attrs IO_TYPE='LVCMOS33' SLEWRATE='SLOW')), (resource spi_psram_4x 1 (subsignal cs (pins-n io F20)) (subsignal clk (pins io J19)) (subsignal dq (pins io J20 G19 G20 H20) (attrs PULLMODE='UP')) (attrs IO_TYPE='LVCMOS33' SLEWRATE='SLOW')), (resource sdram 0 (subsignal clk (pins o D11)) (subsignal clk_en (pins o C11)) (subsignal cs (pins-n o C7)) (subsignal we (pins-n o B6)) (subsignal ras (pins-n o D6)) (subsignal cas (pins-n o A6)) (subsignal ba (pins o A7 C8)) (subsignal a (pins o A8 D9 C9 B9 C14 E17 A12 B12 H17 G18 B8 A11 B11)) (subsignal dq (pins io C5 B5 A5 C6 B10 C10 D10 A9)) (subsignal dqm (pins o A10)) (attrs IO_TYPE='LVCMOS33' SLEWRATE='FAST'))]
connectors = [(connector pmod 0 1=>A15 2=>C16 3=>A14 4=>D16 5=>B15 6=>C15 7=>A13 8=>B13), (connector cartridge 0 9=>C5 10=>B5 11=>A5 12=>C6 13=>B6 14=>A6 15=>D6 16=>C7 17=>A7 18=>C8 19=>B8 20=>A8 21=>D9 22=>C9 23=>B9 24=>A9 25=>D10 26=>C10 27=>B10 28=>A10 29=>D11 30=>C11 31=>B11 32=>A11 33=>G18 34=>H17 35=>B12 36=>A12 37=>E17 38=>C14), (connector sao 0 sda=>B3 scl=>B2 gpio0=>A2 gpio1=>A3 gpio2=>B4 gpio3=>A4), (connector sao 1 sda=>A16 scl=>B17 gpio0=>B18 gpio1=>A17 gpio2=>B16 gpio3=>C17)]
toolchain_prepare(fragment: Fragment, name: str, **kwargs) → BuildPlan

Convert the fragment and constraints recorded in this Platform into a BuildPlan.

toolchain_program(products: BuildProducts, name: str) → None

Extract bitstream for fragment name from products and download it to a target.

class torii_boards.lattice.tinyfpga_ax1.TinyFPGAAX1Platform
device = 'LCMXO2-256HC'
package = 'SG32'
speed = '4'
pretty_name = 'TinyFPGA AX1'
description = 'TinyFPGA AX1 Lattice MachXO2-256 Development Board'
connectors = [(connector gpio 0 1=>13 2=>14 3=>16 4=>17 5=>20 6=>21 7=>23 8=>25 9=>26 10=>27 11=>28 16=>4 17=>5 18=>8 19=>9 20=>10 21=>11 22=>12)]
resources = []
class torii_boards.lattice.tinyfpga_ax2.TinyFPGAAX2Platform
device = 'LCMXO2-1200HC'
package = 'SG32'
speed = '4'
pretty_name = 'TinyFPGA AX2'
description = 'TinyFPGA AX2 Lattice MachXO2-1200 Development Board'
connectors = [(connector gpio 0 1=>13 2=>14 3=>16 4=>17 5=>20 6=>21 7=>23 8=>25 9=>26 10=>27 11=>28 16=>4 17=>5 18=>8 19=>9 20=>10 21=>11 22=>12)]
resources = []
class torii_boards.lattice.tinyfpga_bx.TinyFPGABXPlatform(*, toolchain: Literal['IceStorm', 'LSE-iCECube2', 'Synplify-iCECube2'] = 'IceStorm')
device = 'iCE40LP8K'
package = 'CM81'
default_clk = 'clk16'
pretty_name = 'TinyFPGA BX'
description = 'TinyFPGA BX Lattice iCE40-LP8K Development Board'
resources = [(resource clk16 0 (pins i B2) (clock 16000000.0) (attrs IO_STANDARD='SB_LVCMOS')), (resource led 0 (pins o B3) (attrs IO_STANDARD='SB_LVCMOS')), (resource usb 0 (subsignal d_p (pins io B4)) (subsignal d_n (pins io A4)) (subsignal pullup (pins o A3)) (attrs IO_STANDARD='SB_LVCMOS')), (resource spi_flash_1x 0 (subsignal cs (pins-n o F7)) (subsignal clk (pins o G7)) (subsignal copi (pins o G6)) (subsignal cipo (pins i H7)) (subsignal wp (pins-n o H4)) (subsignal hold (pins-n o J8)) (attrs IO_STANDARD='SB_LVCMOS')), (resource spi_flash_2x 0 (subsignal cs (pins-n o F7)) (subsignal clk (pins o G7)) (subsignal dq (pins io G6 H7)) (attrs IO_STANDARD='SB_LVCMOS')), (resource spi_flash_4x 0 (subsignal cs (pins-n o F7)) (subsignal clk (pins o G7)) (subsignal dq (pins io G6 H7 H4 J8)) (attrs IO_STANDARD='SB_LVCMOS'))]
connectors = [(connector gpio 0 1=>A2 2=>A1 3=>B1 4=>C2 5=>C1 6=>D2 7=>D1 8=>E2 9=>E1 10=>G2 11=>H1 12=>J1 13=>H2 14=>H9 15=>D9 16=>D8 17=>C9 18=>A9 19=>B8 20=>A8 21=>B7 22=>A7 23=>B6 24=>A6 25=>G1 26=>J3 27=>J4 28=>G9 29=>J9 30=>E8 31=>J2)]
toolchain_program(products: BuildProducts, name: str) → None

Extract bitstream for fragment name from products and download it to a target.

class torii_boards.lattice.ulx3s.ULX3S_12F_Platform(*, toolchain: Literal['Trellis', 'Diamond'] = 'Trellis')
device = 'LFE5U-12F'
pretty_name = 'ULXS3-12F'
description = 'Radiona ULXS3-12F Lattice ECP5-12F Development Board'
class torii_boards.lattice.ulx3s.ULX3S_25F_Platform(*, toolchain: Literal['Trellis', 'Diamond'] = 'Trellis')
device = 'LFE5U-25F'
pretty_name = 'ULXS3-24F'
description = 'Radiona ULXS3-25F Lattice ECP5-25F Development Board'
class torii_boards.lattice.ulx3s.ULX3S_45F_Platform(*, toolchain: Literal['Trellis', 'Diamond'] = 'Trellis')
device = 'LFE5U-45F'
pretty_name = 'ULXS3-45F'
description = 'Radiona ULXS3-45F Lattice ECP5-45F Development Board'
class torii_boards.lattice.ulx3s.ULX3S_85F_Platform(*, toolchain: Literal['Trellis', 'Diamond'] = 'Trellis')
device = 'LFE5U-85F'
pretty_name = 'ULXS3-85F'
description = 'Radiona ULXS3-85F Lattice ECP5-85F Development Board'
class torii_boards.lattice.upduino_v1.UpduinoV1Platform(*, toolchain: Literal['IceStorm', 'LSE-iCECube2', 'Synplify-iCECube2'] = 'IceStorm')
device = 'iCE40UP5K'
package = 'SG48'
default_clk = 'SB_HFOSC'
hfosc_div = 0
pretty_name = 'Upduino V1'
description = 'TinyVision Upduino V1 Lattice iCE40-UP5K Development Board'
resources = [(resource led 0 (pins-n o 39) (attrs IO_STANDARD='SB_LVCMOS')), (resource led 1 (pins-n o 40) (attrs IO_STANDARD='SB_LVCMOS')), (resource led 2 (pins-n o 41) (attrs IO_STANDARD='SB_LVCMOS')), (resource led_g 0 (pins-n o 39) (attrs IO_STANDARD='SB_LVCMOS')), (resource led_b 0 (pins-n o 40) (attrs IO_STANDARD='SB_LVCMOS')), (resource led_r 0 (pins-n o 41) (attrs IO_STANDARD='SB_LVCMOS')), (resource spi_flash_1x 0 (subsignal cs (pins-n o 16)) (subsignal clk (pins o 15)) (subsignal copi (pins o 14)) (subsignal cipo (pins i 17)) (attrs IO_STANDARD='SB_LVCMOS')), (resource spi_flash_2x 0 (subsignal cs (pins-n o 16)) (subsignal clk (pins o 15)) (subsignal dq (pins io 14 17)) (attrs IO_STANDARD='SB_LVCMOS'))]
connectors = [(connector j 0 3=>23 4=>25 5=>26 6=>27 7=>32 8=>35 9=>31 10=>37 11=>34 12=>43 13=>36 14=>42 15=>38 16=>28), (connector j 1 1=>12 2=>21 3=>13 4=>19 5=>18 6=>11 7=>9 8=>6 9=>44 10=>4 11=>3 12=>48 13=>45 14=>47 15=>46 16=>2)]
class torii_boards.lattice.upduino_v2.UpduinoV2Platform(*, toolchain: Literal['IceStorm', 'LSE-iCECube2', 'Synplify-iCECube2'] = 'IceStorm')
pretty_name = 'Upduino V2'
description = 'TinyVision Upduino V2 Lattice iCE40-UP5K Development Board'
resources = [(resource led 0 (pins-n o 39) (attrs IO_STANDARD='SB_LVCMOS')), (resource led 1 (pins-n o 40) (attrs IO_STANDARD='SB_LVCMOS')), (resource led 2 (pins-n o 41) (attrs IO_STANDARD='SB_LVCMOS')), (resource led_g 0 (pins-n o 39) (attrs IO_STANDARD='SB_LVCMOS')), (resource led_b 0 (pins-n o 40) (attrs IO_STANDARD='SB_LVCMOS')), (resource led_r 0 (pins-n o 41) (attrs IO_STANDARD='SB_LVCMOS')), (resource spi_flash_1x 0 (subsignal cs (pins-n o 16)) (subsignal clk (pins o 15)) (subsignal copi (pins o 14)) (subsignal cipo (pins i 17)) (attrs IO_STANDARD='SB_LVCMOS')), (resource spi_flash_2x 0 (subsignal cs (pins-n o 16)) (subsignal clk (pins o 15)) (subsignal dq (pins io 14 17)) (attrs IO_STANDARD='SB_LVCMOS')), (resource clk12 0 (pins i 12) (clock 12000000.0) (attrs IO_STANDARD='SB_LVCMOS'))]
toolchain_program(products: BuildProducts, name: str) → None

Extract bitstream for fragment name from products and download it to a target.

class torii_boards.lattice.versa_ecp5_5g.VersaECP55GPlatform(*, toolchain: Literal['Trellis', 'Diamond'] = 'Trellis')
device = 'LFE5UM5G-45F'
pretty_name = 'Versa 5G'
description = 'Lattice Versa 5G ECP5-5G-45F Evaluation Board'
class torii_boards.lattice.versa_ecp5.VersaECP5Platform(*, toolchain: Literal['Trellis', 'Diamond'] = 'Trellis')
device = 'LFE5UM-45F'
package = 'BG381'
speed = '8'
default_clk = 'clk100'
default_rst = 'rst'
pretty_name = 'Versa'
description = 'Lattice Versa ECP5-45F Evaluation Board'
resources = [(resource rst 0 (pins-n i T1) (attrs IO_TYPE='LVCMOS33')), (resource clk100 0 (diffpairs i (p P3) (n P4)) (clock 100000000.0) (attrs IO_TYPE='LVDS')), (resource pclk 0 (diffpairs i (p A4) (n A5)) (attrs IO_TYPE='LVDS')), (resource led 0 (pins-n o E16) (attrs IO_TYPE='LVCMOS25')), (resource led 1 (pins-n o D17) (attrs IO_TYPE='LVCMOS25')), (resource led 2 (pins-n o D18) (attrs IO_TYPE='LVCMOS25')), (resource led 3 (pins-n o E18) (attrs IO_TYPE='LVCMOS25')), (resource led 4 (pins-n o F17) (attrs IO_TYPE='LVCMOS25')), (resource led 5 (pins-n o F18) (attrs IO_TYPE='LVCMOS25')), (resource led 6 (pins-n o E17) (attrs IO_TYPE='LVCMOS25')), (resource led 7 (pins-n o F16) (attrs IO_TYPE='LVCMOS25')), (resource alnum_led 0 (subsignal a (pins-n o M20)) (subsignal b (pins-n o L18)) (subsignal c (pins-n o M19)) (subsignal d (pins-n o L16)) (subsignal e (pins-n o L17)) (subsignal f (pins-n o M18)) (subsignal g (pins-n o N16)) (subsignal h (pins-n o M17)) (subsignal j (pins-n o N18)) (subsignal k (pins-n o P17)) (subsignal l (pins-n o N17)) (subsignal m (pins-n o P16)) (subsignal n (pins-n o R16)) (subsignal p (pins-n o R17)) (subsignal dp (pins-n o U1)) (attrs IO_TYPE='LVCMOS25')), (resource switch 0 (pins i H2) (attrs IO_TYPE='LVCMOS15')), (resource switch 1 (pins i K3) (attrs IO_TYPE='LVCMOS15')), (resource switch 2 (pins i G3) (attrs IO_TYPE='LVCMOS15')), (resource switch 3 (pins i F2) (attrs IO_TYPE='LVCMOS15')), (resource switch 4 (pins i J18) (attrs IO_TYPE='LVCMOS25')), (resource switch 5 (pins i K18) (attrs IO_TYPE='LVCMOS25')), (resource switch 6 (pins i K19) (attrs IO_TYPE='LVCMOS25')), (resource switch 7 (pins i K20) (attrs IO_TYPE='LVCMOS25')), (resource uart 0 (subsignal rx (pins i C11)) (subsignal tx (pins o A11)) (attrs IO_TYPE='LVCMOS33' PULLMODE='UP')), (resource spi_flash_1x 0 (subsignal cs (pins-n o R2)) (subsignal clk (pins o U3)) (subsignal copi (pins o V2)) (subsignal cipo (pins i W2)) (subsignal wp (pins-n o Y2)) (subsignal hold (pins-n o W1)) (attrs IO_TYPE='LVCMOS33')), (resource spi_flash_2x 0 (subsignal cs (pins-n o R2)) (subsignal clk (pins o U3)) (subsignal dq (pins io V2 W2)) (attrs IO_TYPE='LVCMOS33')), (resource spi_flash_4x 0 (subsignal cs (pins-n o R2)) (subsignal clk (pins o U3)) (subsignal dq (pins io V2 W2 Y2 W1)) (attrs IO_TYPE='LVCMOS33')), (resource eth_clk125 0 (pins i L19) (clock 125000000.0) (attrs IO_TYPE='LVCMOS25')), (resource eth_clk125_pll 0 (pins i U16) (clock 125000000.0) (attrs IO_TYPE='LVCMOS25')), (resource eth_rgmii 0 (subsignal rst (pins-n o U17)) (subsignal mdc (pins o T18)) (subsignal mdio (pins io U18)) (subsignal tx_clk (pins o P19)) (subsignal tx_ctl (pins o R20)) (subsignal tx_data (pins o N19 N20 P18 P20)) (subsignal rx_clk (pins i L20)) (subsignal rx_ctl (pins i U19)) (subsignal rx_data (pins i T20 U20 T19 R18)) (attrs IO_TYPE='LVCMOS25')), (resource eth_sgmii 0 (subsignal rst (pins-n o U17) (attrs IO_TYPE='LVCMOS25')) (subsignal mdc (pins o T18) (attrs IO_TYPE='LVCMOS25')) (subsignal mdio (pins io U18) (attrs IO_TYPE='LVCMOS25')) (subsignal tx (diffpairs o (p W13) (n W14))) (subsignal rx (diffpairs i (p Y14) (n Y15)))), (resource eth_clk125 1 (pins i J20) (clock 125000000.0) (attrs IO_TYPE='LVCMOS25')), (resource eth_clk125_pll 1 (pins i C18) (clock 125000000.0) (attrs IO_TYPE='LVCMOS25')), (resource eth_rgmii 1 (subsignal rst (pins-n o F20)) (subsignal mdc (pins o G19)) (subsignal mdio (pins io H20)) (subsignal tx_clk (pins o C20)) (subsignal tx_ctrl (pins o E19)) (subsignal tx_data (pins o J17 J16 D19 D20)) (subsignal rx_clk (pins i J19)) (subsignal rx_ctrl (pins i F19)) (subsignal rx_data (pins i G18 G16 H18 H17)) (attrs IO_TYPE='LVCMOS25')), (resource eth_sgmii 1 (subsignal rst (pins-n o F20) (attrs IO_TYPE='LVCMOS25')) (subsignal mdc (pins o G19) (attrs IO_TYPE='LVCMOS25')) (subsignal mdio (pins io H20) (attrs IO_TYPE='LVCMOS25')) (subsignal tx (diffpairs o (p W17) (n W18))) (subsignal rx (diffpairs i (p Y16) (n Y17)))), (resource ddr3 0 (subsignal rst (pins-n o N4)) (subsignal clk (diffpairs o (p M4) (n N5)) (attrs IO_TYPE='SSTL135D_I')) (subsignal clk_en (pins o N2)) (subsignal cs (pins-n o K1)) (subsignal we (pins-n o M1)) (subsignal ras (pins-n o P1)) (subsignal cas (pins-n o L1)) (subsignal a (pins o P2 C4 E5 F5 B3 F4 B5 E4 C5 E3 D5 B4 C3)) (subsignal ba (pins o P5 N3 M3)) (subsignal dqs (diffpairs io (p K2 H4) (n J1 G5)) (attrs IO_TYPE='SSTL135D_I' DIFFRESISTOR='100' TERMINATION='OFF')) (subsignal dq (pins io L5 F1 K4 G1 L4 H1 G2 J3 D1 C1 E2 C2 F3 A2 E1 B1)) (subsignal dm (pins o J4 H5)) (subsignal odt (pins o L2)) (attrs TERMINATION='75' IO_TYPE='SSTL135_I' SLEWRATE='FAST'))]
connectors = [(connector expcon 1 4=>B19 5=>B12 6=>B9 7=>E6 8=>D6 9=>E7 10=>D7 11=>B11 12=>B6 13=>E9 14=>D9 15=>B8 16=>C8 17=>D8 18=>E8 19=>C7 20=>C6), (connector expcon 2 1=>A8 3=>A12 4=>A13 5=>B13 6=>C13 7=>D13 8=>E13 9=>A14 10=>C14 11=>D14 12=>E14 13=>D11 14=>C10 15=>A9 16=>B10 17=>D12 18=>E12 21=>B15 23=>C15 25=>D15 27=>E15 28=>A16 29=>B16 31=>C16 32=>D16 33=>B17 35=>C17 36=>A17 37=>B18 38=>A7 39=>A18)]
property file_templates: Dict[str, str]
toolchain_program(products: BuildProducts, name: str) → None

Extract bitstream for fragment name from products and download it to a target.